3A, 2MHz, Synchronous Step-Down DC/DC Converteridesyn.com/PDF/iD8259.pdf · 3A, 2MHz, Synchronous Step-Down DC/DC Converter ... General Description The iD8259 is a constant-frequency,

iDESYN iD8259

3A, 2MHz, Synchronous

Step-Down DC/DC Converter

Apr. 2011 1 V0.4

General Description The iD8259 is a constant-frequency, synchronous,

step-down DC/DC converter. Intended for medium

power applications, it operates from a 2.5V to 5.5V

input voltage range and has a user configurable

operating frequency up to 2MHz, allowing the use of

tiny, low cost capacitors and inductors 2mm or less in

height. The output voltage is adjustable from 0.8V to

5V. The Internal synchronous 0.11Ω power switches

are capable of delivering up to 3A output current

ratings with high efficiency. The iD8259’s current mode

architecture and external compensation allow the

transient response to be optimized over a wide range

of loads and output capacitors.

To further maximize battery life, the P-channel

MOSFET is turned on continuously in dropout (100%

duty cycle). The no-load quiescent current is only

100μA. In shutdown, the device draws <1μA.

Ordering Information

iD8259 -

PackageFEA:TDFN-10P80:PSOP-8

Output Voltage Voltage CodeAdjustable AD

TapingR: Tape and Reel

Applications Wireless LAN Power

Notebook Computers

Digital Cameras

Cellular Phones

Board Mounted Power Supplies

Features Uses Tiny Capacitors and Inductor

High Frequency Operation: Up to 2MHz

Up to 3A of output current

No Schottky Diode Required

Low RDS(ON) Internal Switches: 0.110Ω

High Efficiency: Up to 95%

VIN: 2.5V to 5.5V

Stable with Ceramic Capacitors

Current Mode Operation for Excellent Line and

Load Transient Response

Short-Circuit Protected

Low Dropout Operation: 100% Duty Cycle

Low Shutdown Current: ≤ 1μA

Low Quiescent Current: 100μA

Output Voltages from 0.8V to 5V

Low Noise Pulse-Skipping Operation

RoHS / Green Compliant

Marking Information For marking information, please contact our sales

representative directly or through distributor around

your location.

iDESYN iD8259

Apr. 2011 2 V0.4

Typical Application Circuit

(Adjustable Operation)

Absolute Maximum Ratings Recommended Operating Conditions Supply Voltage VIN 6V Input Voltage VIN 2.5V to 5.5V

Power Dissipation, PD @ TA=25°C Junction Temperature -40°C to 125°C

TDFN -10 L (3x3) 2.083W Ambient Operating Temperature -40°C to 85°C

PSOP-8 1.33W

Thermal Resistance, θja

TDFN -10L (3x3) 48°C/W

PSOP-8 75°C/W

Lead Temperature 260°C

Storage Temperature -65°C to 150°C

ESD Susceptibility

HBM (Human Body Mode) 2kV

MM (Machine Mode) 200V

iDESYN iD8259

Apr. 2011 3 V0.4

Pin Configurations

SHDN/RT

GND

SW

SW

1

2

3

4

(Top View)TDFN-10

Exposed Pad on Backside.Connect to Pin 5.

PGND 5

10

9

8

7

6

COMP

FB

VDD

PVDD

PVDD11

SHDN/RT

GND

SW

PGND

COMP

FB

VDD

PVDD

1

2

3

4 5

6

7

8

(Top View)PSOP-8

Exposed Pad on Backside.Connect to Pin 4.

9

Pin Description TDFN-10 PSOP-8 Name Description

1 1 SHDN/RT Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. Forcing this pin to VDD causes the device to be shutdown.

2 2 GND Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point.

3 , 4 3 SW Internal Power MOSFET Switches Output. Connect this pin to the inductor.

5 4 PGND Power Ground. Connect this pin close to the (−) terminal of CIN and COUT.

6 , 7 5 PVDD Power Input Supply. Decouple this pin to PGND with a capacitor.

8 6 VDD Signal Input Supply. Decouple this pin to GND with a capacitor. Normally VDD is equal to PVDD.

9 7 FB Feedback Pin. Receives the feedback voltage from a resistive divider connected across the output.

10 8 COMP Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Connect external compensation elements to this pin to stabilize the control loop.

11 (Exposed Pad)

9 (Exposed Pad) NC No Internal Connection. The exposed pad must be soldered to a large

PCB and connected to GND for maximum power dissipation.

iDESYN iD8259

Apr. 2011 4 V0.4

Function Block Diagram

SW

PVDD

PGND

Driver

Current Sense

Control Logic

0.8 V

OSC

SHDN/RT

SD

UVLO Over Temperature Detector

Current Limit Detector

VFB

Voltage Reference

GNDVDD COMP

PWM Comparator

Shut down

Error Amp.

Σ

iDESYN iD8259

Apr. 2011 5 V0.4

Electrical Characteristics (Otherwise specifications are at TA = 25°C. VIN = 3.3V, ROSC = 330kΩ unless otherwise specified.)

Parameters Symbol Condition Min Typ Max UnitsOperating Voltage Range VIN 2.5 5.5 V Feedback Pin Input Current IFB ±0.1 % Feedback Voltage VFB 0.776 0.8 0.824 V

Reference Voltage Line Regulation ΔVLINEREG VIN=2.5V to 5.5V 0.04 0.4 %/V

Output Voltage Load Regulation ΔVLOADREG 0mA<ILOAD<2A 0.25 %

Active Mode VFB=0.75V 280 400 μA Shutdown

IS VSHDN/RT=3.3V 0.1 1 μA

Shutdown Threshold VSHDN/RT VIN-0.6 VIN-0.4 V

ROSC=330kΩ 0.8 1.2 Oscillator Frequency FOSC

Switching Frequency 0.3 1

2 MHz

Peak Switch Current Limit ILIM VCOMP=1.27V 4.8 A Top Switch On-Resistance VIN=3.3V, ISW=1A 0.11 0.15 Bottom Switch On-Resistance

RDS(ON) VIN=3.3V, ISW=1A 0.11 0.15

Ω

Switch Leakage Current ISW(LKG) VIN=6V, VCOMP=0V, VFB=0V 0.01 1 μA Undervoltage Lockout Threshold VUVLO VIN Ramping Down 1.6 V

Compensation Table List CIN = 22μF (X5R ceramic), COUT = 22μFx2 (X5R ceramic), C1 = 22pF (X5R ceramic), FOSC = 1MHz, TA = 25°C.

Input Voltage (V) Output Voltage (V) Inductor (μH) CCOMP (F) RCOMP (kΩ) 5 3.3 3.3 330p 47 5 2.8 3.3 330p 47 5 2.5 3.3 330p 47 5 1.8 2.2 330p 16 5 1.5 2.2 330p 20 5 1.2 2.2 330p 20 5 1.0 2.2 1n 30

iDESYN iD8259

Apr. 2011 6 V0.4

Typical Operating Characteristics

0

10

20

30

40

50

60

70

80

90

100

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 0

10

20

30

40

50

60

70

80

90

100

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

0.85

0 0.5 1 1.5 2 2.5 3

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0 0.5 1 1.5 2 2.5 3

0.74

0.75

0.76

0.77

0.78

0.79

0.8

0.81

0.82

-40 -20 0 20 40 60 80 100 120 140

0.75

0.76

0.77

0.78

0.79

0.8

0.81

0.82

-40 -20 0 20 40 60 80 100 120 140

Output Current (A)

Effic

ienc

y (%

)

Efficiency vs. Output Current

Output Current (A)

Effic

ienc

y(%

)

Efficiency vs. Output Current

VOUT=3.3V, L=2.2μHROSC=330kΩ

CCOMP=330pFRCOMP=47kΩ

VOUT=1.2V, L=2.2μHROSC=330kΩ

CCOMP=330pFRCOMP=20kΩ

VIN=4.2V VIN=5.0V

VIN=3.3V

VIN=2.5V

Feedback Voltage vs. Output Current Feedback Voltage vs. Output Current

Output Current (A)

Feed

back

Vol

tage

(V)

Output Current (A)

Feed

back

Vol

tage

(V)

Feed

back

Vol

tage

(V)

Feed

back

Vol

tage

(V)

Temperature (˚C) Temperature (˚C)

Feedback Voltage vs. Temperature Feedback Voltage vs. Temperature

VIN=5.0VVOUT=1.2V, L=2.2μH

IOUT=1A, ROSC=330kΩ

VIN=5.0V, VOUT=1.2VL=2.2μH, ROSC=330kΩ

VIN=5.0V, VOUT=3.3VL=2.2μH, ROSC=330kΩ

VIN=5.0VVOUT=3.3V, L=2.2μH

IOUT=1A, ROSC=330kΩ

iDESYN iD8259

Apr. 2011 7 V0.4

0.6

0.7

0.8

0.9

1

1.1

1.2

2.5 3 3.5 4 4.5 5 5.5

0.6

0.7

0.8

0.9

1

1.1

1.2

4 4.3 4.6 4.9 5.2 5.5

0.6

0.7

0.8

0.9

1

1.1

1.2

-40 -20 0 20 40 60 80 100 120 140

0.6

0.7

0.8

0.9

1

1.1

1.2

-40 -20 0 20 40 60 80 100 120 140

0

20

40

60

80

100

120

2.5 3 3.5 4 4.5 5 5.5

0

20

40

60

80

100

120

-40 -20 0 20 40 60 80 100 120 140

Input Voltage (V)

Oscillator Frequency vs. Input Voltage

Input Voltage (V)

Oscillator Frequency vs. Input Voltage

Osc

illat

or F

requ

ency

(MH

z)

Osc

illat

or F

requ

ency

(MH

z)

Temperature (˚C)

Osc

illat

or F

requ

ency

(MH

z)

Temperature (˚C)

Osc

illat

or F

requ

ency

(MH

z)

Oscillator Frequency vs. Temperature Oscillator Frequency vs. Temperature

VOUT=1.2V, IOUT=1AL=2.2μH, ROSC=330kΩ

Input Voltage (V)

Sup

ply

Cur

rent

(μA)

Sup

ply

Cur

rent

(μA)

Supply Current vs. Input Voltage Supply Current vs. Temperature

Temperature (˚C)

VOUT=1.2V, IOUT=0AL=2.2μH, ROSC=330kΩ

VIN=5.0V, VOUT=1.2V, IOUT=0AL=2.2μH, ROSC=330kΩ

VOUT=3.3V, IOUT=1AL=2.2μH, ROSC=330kΩ

VIN=5.0V, VOUT=1.2V, IOUT=1AL=2.2μH, ROSC=330kΩ

VIN=5.0V, VOUT=3.3V, IOUT=1AL=2.2μH, ROSC=330kΩ

iDESYN iD8259

Apr. 2011 8 V0.4

0

20

40

60

80

100

2.5 3 3.5 4 4.5 5 5.5

0

20

40

60

80

100

-40 -20 0 20 40 60 80 100 120 140

0

0.1

0.2

0.3

0.4

0.5

2.5 3 3.5 4 4.5 5 5.5

0

0.4

0.8

1.2

1.6

2

-40 -20 0 20 40 60 80 100 120 140

3

4

5

6

7

8

9

2.5 3 3.5 4 4.5 5 5.5

0

0.1

0.2

0.3

0.4

0.5

2.5 3 3.5 4 4.5 5 5.5

Input Voltage (V) Temperature (˚C)

Qui

esce

nt C

urre

nt (μ

A)

Qui

esce

nt C

urre

nt (μ

A)

Quiescent Current vs. Input Voltage Quiescent Current vs. Temperature

No Switching VIN=5.0V, No Switching

Input Voltage (V)

Shu

tdow

n C

urre

nt (μ

A)

Shu

tdow

n C

urre

nt (μ

A)

Shutdown Current vs. Input Voltage Shutdown Current vs. Temperature

Temperature (˚C)

SHDN/RT through ROSC connected to VIN VIN=5.0V, SHDN/RT through ROSCconnected to VIN

Input Voltage (V)

Cur

rent

Lim

it (A

)

Current Limit vs. Input Voltage

VOUT connected to GND

Input Voltage (V)

RD

S (O

N) (Ω

)

RDS(ON) vs. Input Voltage

VIN =5.0V, ISW=1.0A, FB connected to GND

iDESYN iD8259

Apr. 2011 9 V0.4

Short Circuit Test

VSW (DC) (2V/Div)

ISW (DC) (500mA/Div)

Time (1μs/Div)

VOUT (AC) (20mV/Div)

VIN=5.0V, VOUT=3.3V, L=2.2μH, IOUT=0.25A ROSC=330kΩ, C1=22pF, CCOMP=330pF, RCOMP=47kΩ

Light Load Operating

VSW (DC) (2V/Div)

ISW (DC) (2A/Div)

VOUT (AC) (20mV/Div)

VIN=5.0V, VOUT=3.3V, L=2.2μH, IOUT=3AROSC=330kΩ, C1=22pF,CCOMP=330pF, RCOMP=47kΩ

Time (1μs/Div)

Heavy Load Operating

VSW (DC) (2V/Div)

ISW (DC) (2A/Div)

Time (1μs/Div)

VOUT (AC) (20mV/Div)

Light Load Operating

Heavy Load Operating

VIN=5.0V, VOUT=1.2V, L=2.2μH, IOUT=3AROSC=330kΩ, C1=22pF, CCOMP=330pF, RCOMP=20kΩ

UVLO

VSW (DC) (5V/Div)

ISW (DC) (2A/Div)

Time (5μs/Div)

6.1A

VIN=5.0V, VOUT=1.2V, L=3.3μHVOUT Connected to GND

68.2kHz

VSW (DC) (2V/Div)

ISW (DC) (500mA/Div)

Time (1μs/Div)

VOUT (AC) (20mV/Div)

VIN=5.0V, VOUT=1.2V, L=2.2μH, IOUT=0.25A ROSC=330kΩ, C1=22pF, CCOMP=330pF, RCOMP=20kΩ

VIN (DC) (2V/Div)

VSW (DC) (2V/Div)

Time (2.5ms/Div)

1.76V

VIN=5.0V, VOUT=1.2V, L=2.2μH, IOUT=0.3A ROSC=330kΩ

iDESYN iD8259

Apr. 2011 10 V0.4

VOUT (AC) (20mV/Div)

IOUT (DC) (1A/Div)

Time (250μs/Div)

Load Transient Response

VDROP=25.6mV, VP-P=58.4mV

VIN=5.0V, VOUT=1.2V, L=2.2μH,IOUT=0A~3AROSC=330kΩ, C1=22pF, CCOMP=330pF, RCOMP=20kΩ

VEN (DC) (5V/Div)

IIN (DC) (1A/Div)

VOUT (DC) (2V/Div)

Time (40μs/Div)

Power on From SHDN

VIN=5.0V, VOUT=1.2V, L=2.2μH, IOUT=3A, ROSC=330kΩ

Power on From SHDN

VEN (DC) (5V/Div)

IIN (DC) (1A/Div)

VOUT (DC) (1V/Div)

VIN=5.0V, VOUT=1.2V, L=2.2μH, IOUT=3A, ROSC=330kΩ

Time (4ms/Div)

(Resistive Load)

VIN (DC) (5V/Div)

IIN (DC) (2A/Div)

VOUT (DC) (2V/Div)

Time (40μs/Div)

Power on From VIN

VIN=5.0V, VOUT=3.3V, L=2.2μH, IOUT=3A, ROSC=330kΩ

Power on From VIN

(Resistive Load)

VOUT (AC) (50mV/Div)

IOUT (DC) (1A/Div)

Time (250μs/Div)

Load Transient Response

VDROP=88mV, VP-P=142mV

VIN=5.0V, VOUT=3.3V, L=2.2μH,IOUT=0A~3AROSC=330kΩ, C1=22pF, CCOMP=330pF, RCOMP=47kΩ

VIN (DC) (5V/Div)

IIN (DC) (1A/Div)

VOUT (DC) (1V/Div)

(Resistive Load)

Time (4ms/Div)

VIN=5.0V, VOUT=3.3V, L=2.2μH, IOUT=3A, ROSC=330kΩ(Resistive Load)

iDESYN iD8259

Apr. 2011 11 V0.4

Application Note External component selection is driven by the load requirement, and begins with the selection of the inductor L1.

Once L1 is chosen, CIN and COUT can be selected.

Operating Frequency

Selection of the operating frequency is a trade-off between efficiency and component size. High frequency

operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves

efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to

maintain low output ripple voltage.

The operating frequency of the iD8259 is determined by an external resistor that is connected between the

SHDN/RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an

internal timing capacitor within the oscillator. The ROSC resistor value can be determined by examining the

frequency vs. ROSC curve.

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

100 200 300 400 500 600 700 800 900 1000

Inductor Selection

Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple

current. The inductor ripple current ΔIL decreases with higher inductance and increases with higher VIN or VOUT:

⎟⎟⎠

⎞⎜⎜⎝

⎛−×

×=Δ

IN

OUT

O

OUTL

VV

LfV

I 1

Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple, greater

core losses, and lower output current capability. A reasonable starting point for setting ripple current is ΔIL =

0.4 ×IOUT(MAX), where IOUT(MAX) is 1A. The largest ripple current ΔIL occurs at the maximum input voltage. To

guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according

to the following equation:

⎟⎟⎠

⎞⎜⎜⎝

⎛−×

×Δ=

)(

1MAXIN

OUT

OL

OUT

VV

fIV

L

ROSC (kΩ)

Freq

uenc

y (M

Hz)

iDESYN iD8259

Apr. 2011 12 V0.4

Inductor Core Selection

Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid

or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost

more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to

use often depends more on the price vs. size requirements and any radiated field/EMI requirements than on what

the iD8259 requires to operate.

Representative Surface Mount Inductors

MANU-FACTURER PART NUMBER VALUE MAX DC CURRENT DCR HEIGHT

Toko A914BYW-2R2M-D52LC 2.2μH 2.05A 49mΩ 2mm Coilcraft D01608C-222 2.2μH 2.3A 70mΩ 3mm

Taiyo Yuden N05DB2R2M 2.2μH 2.9A 32mΩ 2.8mm Murata LQN6C2R2M04 2.2μH 3.2A 24mΩ 5mm

Input Capacitor (CIN) Selection

In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/VIN.

To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum

RMS current must be used. The maximum RMS capacitor current is given by:

( )IN

OUTINOUTMAXRMS V

VVVII

−≈

where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current,

IMAX = ILIM – ΔIL/2.

This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case is commonly used to

design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple

current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to

meet the size or height requirements of the design. An additional 0.1μF to 1μF ceramic capacitor is also

recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution.

Output Capacitor (COUT) Selection

The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically,

once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is

determined by:

⎟⎟⎠

⎞⎜⎜⎝

⎛×

+Δ≈ΔOUTO

LOUT CfESRIV

81

iDESYN iD8259

Apr. 2011 13 V0.4

Where fO = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. The output

ripple is highest at maximum input voltage since ΔIL increases with input voltage. With ΔIL = 0.3 × ILIM the output

ripple will be less than 100mV at maximum VIN and fO = 1MHz with:

ESRCOUT < 150mΩ

Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P)

requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be

paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum

electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. The

OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any

aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very

low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance

density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power

supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging

from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and is often used in extremely

cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability.

Ceramic capacitors have the lowest ESR and cost but also have the lowest capacitance density, a high voltage and

temperature coefficient and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along

with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic specialty polymer

(SP) capacitors. In most cases, 0.1μF to 1μF of ceramic capacitors should also be placed close to the iD8259 in

parallel with the main capacitors for high frequency decoupling.

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting

for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop

stability problems. Solid tantalum capacitor ESR generates a loop “zero” at 5kHz to 50kHz that is instrumental in

giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually

resonate with their ESL before ESR becomes effective. Also, ceramic caps are prone to temperature effects which

requires the designer to check loop stability over the operating temperature range. To minimize their large

temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of

ceramic capacitors is available from Taiyo Yuden, TDK and Murata.

Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used

at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the

output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop

instability. At worst, the ringing at the input can be large enough to damage the part.

Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage

requirement. During a load step, the output capacitor must instantaneously supply the current to support the load

until the feedback loop raises the switch current enough to support the load. The time required for the feedback

loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4

iDESYN iD8259

Apr. 2011 14 V0.4

cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output

droop, VDROOP, is usually about 2 to 3 times the linear drop of the first cycle. Thus, a good place to start is with the

output capacitor size of approximately:

DROOPO

OUTOUT Vf

IC

×Δ

≈ 5.2

More capacitance may be required depending on the duty cycle and load step requirements.

In most applications, the input capacitor is merely required to supply high frequency bypassing, since the

impedance to the supply is very low. A 10μF ceramic capacitor is usually enough for these conditions.

Setting the Output Voltage

The iD8259 develops a 0.8V reference voltage between the feedback pin, VFB, and the signal ground as shown in

figure. The output voltage is set by a resistive divider according to the following formula:

⎟⎠⎞

⎜⎝⎛ +≅

2118.0

RRVVOUT

Keeping the current small (<5μA) in these resistors maximizes efficiency, but making them too small may allow

stray capacitance to cause noise problems and reduce the phase margin of the error amp loop.

To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to

route the VFB line away from noise sources, such as the inductor or the SW line.

FB

GNDiD 8259

R1

R2

VOUT

Shutdown

The SHDN/RT pin is a dual purpose pin that sets the oscillator frequency and provides a means to shut down the

iD8259. This pin can be interfaced with control logic in several ways, as shown in figure.

iDESYN iD8259

Apr. 2011 15 V0.4

Efficiency Considerations

The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage of input power.

Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the

losses in iD8259 circuits: 1) iD8259 VIN current, 2) switching losses, 3) I2R losses, 4) other losses.

1) The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver

and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load.

2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results

from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to

high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that

is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB

are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to

VIN and thus their effects will be more pronounced at higher supply voltages.

3) I2R Losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In

continuous mode, the average output current flowing through inductor L is “chopped” between the internal top and

bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET

RDS(ON) and the duty cycle (D) as follows:

RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)

The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics

curves. Thus, to obtain I2R losses:

I2R losses = IOUT2(RSW + RL)

4) Other “hidden” losses such as copper trace and internal battery resistances can account for additional efficiency

degradations in portable systems. It is very important to include these “system” level losses in the design of a

system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate

charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses

during dead-time and inductor core losses generally account for less than 2% total additional loss.

Thermal Considerations

In a majority of applications, the iD8259 does not dissipate much heat due to its high efficiency. However, in

applications where the iD8259 is running at high ambient temperature with low supply voltage and high duty cycles,

such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction

temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become

high impedance.

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Apr. 2011 16 V0.4

To avoid the iD8259 from exceeding the maximum junction temperature, the user will need to do some thermal

analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum

junction temperature of the part. The temperature rise is given by:

TRISE = PD • θJA

where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to

the ambient temperature.

The junction temperature, TJ, is given by:

TJ = TRISE + TAMBIENT

As an example, consider the case when the iD8259 is in dropout at an input voltage of 3.3V with a load current of

1A. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the P-

channel switch is 0.11Ω. Therefore, power dissipated by the part is:

PD = I2 • RDS(ON) = 110mW

The DD8 package junction-to-ambient thermal resistance, θJA, will be in the range of about 48°C/W. Therefore, the

junction temperature of the regulator operating in a 70°C ambient temperature is approximately:

TJ = 0.11 • 48 + 70 = 75.28°C

Remembering that the above junction temperature is obtained from an RDS(ON) at 25°C, we might recalculate the

junction temperature based on a higher RDS(ON) since it increases with temperature. However, we can safely

assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125°C.

0

0.5

1

1.5

2

2.5

-50 -25 0 25 50 75 100 125

TDFN-10

PSOP-8

Ambient Temperature (°C)

Pow

er D

issi

patio

n (W

)

Maximum Power Dissipation

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Apr. 2011 17 V0.4

Layout Guide Follow the PCB layout guidelines for optimal performance of iD8259.

1. In order to stabilize VIN’s Voltage level, we recommend that’s a bypass capacitor as close as possible to the VIN

and GND Pins. That’s provides the AC current into the internal power MOSFETs.

2. Mount each external component as close as possible to the IC.

3. Traces the shortest connecting or place can be reduce the circuit impedance to close on the IC and use the

thick.

4. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be

segregated with all small-signal components returning to the GND pin at one point that is then connected to the

PGND pin close to the IC. The exposed pad should be connected to GND.

5. SW node is with high frequency voltage swing and should be kept small area. Keep all sensitive small-signal

nodes away from SW node to prevent stray capacitive noise pick-up.

6. Connect the FB pin directly to the feedback resistors. The resistor divider must be connected between VOUT

and GND.

2

1

5

9

10

8

6

SW

PGND

SHDN/RT

GND

VDD

PVDD

COMP

FB

GNDR1R2 C1

L1

ROSC

RTH

CTH

COUT X2

CIN

iD8259

7

3

4 PVDD

SW

CIN must be placedbetween PVDD, VDD andGND as closer as Possible.SW should be connected

to Inductor by wide andshort trace, keepsensitive compontentsaway from this trace.

FB node copper area should be minimized and keep far away from noise sources (SW, PVDD, VDD).

COUT must be near iD8259.

The exposed pad and GND, should be connected to a strong ground plane for heat sinking and noise prevention.

The resistor divider, R1 and R2, must be connected between the (+) plate of COUT and a ground line terminated near GND (Pin 2).

PCB Layout Guide (TDFN-10)

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Apr. 2011 18 V0.4

SW

PGND

SHDN/RT

GND

VDD

PVDD

COMP

FBR1R2 C1

L1

ROSC

RTH

CTH

COUT x2

CIN

iD8259

CIN must be placedbetween PVDD, VDD and GND as closer as Possible.SW should be connected

to Inductor by wide andshort trace, keepsensitive compontentsaway from this trace.

FB node copper area should be minimized and keep far away from noise sources (SW, PVDD).

COUT must be near iD8259.

The exposed pad and GND should be connected to a strong ground plane for heat sinking and noise prevention.

The resistor divider, R1 and R2, must be connected between the (+) plate of COUT and a ground line terminated near GND (Pin 2).

1

2

3

4

8

7

6

5

GND

PCB Layout Guide (PSOP-8)

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Apr. 2011 19 V0.4

Packaging

TDFN-10

DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCH SYMBOLS

MIN NOM MAX MIN NOM MAX A 0.70 0.75 0.80 0.028 0.029 0.031

A1 0.00 0.01 0.03 0.000 0.0004 0.0012 A3 --- 0.2 REF --- --- 0.008 --- b 0.18 0.23 0.28 0.0071 0.009 0.011 D 2.95 3.0 BSC 3.03 0.116 0.118 0.119

D1 --- 2.2 BSC --- --- 0.087 --- E 2.85 3.0 BSC 3.15 0.116 0.118 0.119

E1 --- 1.6 BSC --- --- 0.063 --- e --- 0.5BSC --- --- 0.020 --- L 0.30 0.40 0.50 0.012 0.016 0.020 θ -12° --- 0° -12° --- ---

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Apr. 2011 20 V0.4

PSOP-8

DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCH SYMBOLS

MIN NOM MAX MIN NOM MAX A 1.40 1.50 1.60 0.055 0.059 0.063

A1 0.00 --- 0.10 0.000 --- 0.004 A2 --- 1.45 --- --- 0.057 --- B 0.33 --- 0.51 0.013 --- 0.020 C 0.19 --- 0.25 0.007 --- 0.010 D 4.80 --- 5.00 0.189 --- 0.197

D2 3.20 3.30 3.40 0.126 0.130 0.134 E 3.80 3.90 4.00 0.150 0.153 0.157

E2 2.30 2.40 2.50 0.091 0.095 0.099 e --- 1.27 --- --- 0.050 --- H 5.80 6.00 6.20 0.228 0.236 0.244 L 0.40 --- 1.27 0.016 --- 0.050 y --- --- 0.10 --- --- 0.004 θ 0° --- 8° 0° --- 8°

L1-L1’ --- --- 0.12 --- --- 0.005 L1 1.04REF 0.041REF

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Apr. 2011 21 V0.4

Footprint

TDFN-10

Footprint Dimension (mm) Package

P A B C D Sx Sy M Tolerance

DNF-10 (3x3) 0.50 3.80 2.10 0.85 0.30 2.50 1.50 2.30 ±0.030

PSOP-8

Footprint Dimension (mm)

Package Number of PIN P A B C D Sx Sy M

Tolerance

2.30 2.30 PSOP-8 8 1.27 6.80 4.20 1.30 0.70 3.40 2.40 4.51 ±0.10