37161841-18923718-Logic-Design

Nguyen Thanh KienDepartment of Computer EngineeringFaculty of Information TechnologyHanoi University of Technology

Digital Logic Design

Page 2

About

Author: Nguyen Thanh Kien

Office:

Department of Computer Engineering

Faculty of Information Technology

Hanoi University of Technology

Mobile: +84 983 588 135

Email: [email protected]

[email protected]

ftp://dce.hut.edu.vn/kiennt

mailto:[email protected]

mailto:[email protected]

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Content

1. Introduction

2. Function Minimization Methods

3. Larger Combinational Systems

4. Sequential Systems

5. Hardware Design Languages

Page 4

Acknowledge

The following materials are used as reference for this slide:

– “Logic Circuits” slide, Dr. Trinh Van Loan.

– Introduction to Logic Design, 2nd Ed, Alan B. Marcovitz, Mc. Graw Hill,2005

– Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott, World Scientific, 1998

Page 5

Reference textbooks

Introduction to Logic Design, 2nd Ed,, Alan B, Marcovitz, Mc. Graw Hill,2005

Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott, World Scientific, 1998

Page 6

Grading policy

Homework: 20%

Lab work: 20%

Midterm: 30%

Final Exam (multichoice and writing): 30%

Page 7

1. Introduction

1.1. Review of Number Systems

1.2. Switching Algebra and Logic Circuits

Page 8

Chapter 1. Introduction

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1.1.1 Number Representation

1.1.2 Binary Addition

1.1.3 Signed Numbers

1.1.4 Binary Subtraction

1.1.5 Binary Coded Decimal (BCD)

1.1.6 Other Codes

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1.1.6 Other Codes

Page 11

1.1.1. Number Representation

Numbers are normally written using a positional number system:

– Base/radix: b (the number of digits)

– Digits: 0..(b-1)

• 0 ≤ ai ≤ (b-1)

– Binary: b=2, digits:0,1

– Decimal: b=10, digits: 0,1,2,3,4,5,6,7,8,9

– Octal: b=8, digits: 0,1,2,3,4,5,6,7

– Hexadecimal: b=16, digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

mnnnb aaaaaaaaN −−−−−= ....... 210121)(

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mnnnb aaaaaaaaN −−−−−= ....... 210121)(

mm

nn

nn babababababaN −

−−

−−

− +++++++= ............ 11

00

11

11)10(

∑−=

=n

mi

ii baN .)10(

11101.11(2) = 1x24+1x23+1x22+0x21+1x20+1x2-1+1x2-2= 29.75(10)

Page 13


Decimal:

– b=10

– Digits: 0,1,2,3,4,5,6,7,8,9

– Eg:

539.45(10) = 5x102+3x101+9x100+4x10-1+5x10-2

mnnn aaaaaaaaN −−−−−= ....... 210121)10( ai = 0..9

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Binary:

– b=2

– Digits: 0,1

– Eg:

1011.011(2) = 11 + 0*2-1 + 1*2-2+1*2-3=11 + 0 + 0.25 + 0.125

= 11.375(10)

mnnn aaaaaaaaN −−−−−= ....... 210121)2( ai = 0,1

bit – binary digit

∑−=

=n

mi

iiaN 2.)10(

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Binary (cnt’)– n-bit binary number can represent which range?

• an-1...a1a0 from 0 to 2n-1

– MSB – Most Significant Bit

– LSB – Least Significant Bit

0001 = 1 1001 = 9

0010 = 2 1010 = 10

0011 = 3 1011 = 11

0100 = 4 1100 = 12

0101 = 5 1101 = 13

0110 = 6 1110 = 14

0111 = 7 1111 = 15

1000 = 8

Page 16


Octal:

– b=8

– Digits: 0,1,2,3,4,5,6,7

– Eg:

503.071(8) = 5x82 + 0x81 + 3x80 + 0x8-1 + 7x8-2 + 1x8-3

mnn aaaaaaaN −−−−= ....... 21011)8(

ai = 0..7

Hexadecimal:

– b=16

– Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

– Eg:

1010 0011(2)= A3(16)

503.071(16) = 5x162 + 0x161 + 3x160 + 0x16-1 + 7x16-2 + 1x16-3

ai = 0..F

mnn aaaaaaaN −−−−= ....... 21011)16(

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Convert from base b to base 10

Base b to base 10 conversion

Eg:0

– 1010.11(2)= 10.75

– 1010.11(8)= 0*80+1*81+0*82+1*83 + 1*8-

1+1*8-2 = 0+8+0+512+0.125+0.015625

– A12(16)= 10572 = 2*160 + 1*161 + 10*162 = 2 + 16 + 2560= 2578

mnnnb aaaaaaaaN −−−−−= ....... 210121)(

mm

nn

nn babababababaN −

−−

−−

− +++++++= ............ 11

00

11

11)10(

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110.011(2)=?(10) 6.375

110.011(8)=?(10) 72.0175

110.011(16)=?(10) 272.039...

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Convert from base 10 to base b

Base 10 to base b conversion

– For integer part:

• Divide integer part by b until the result is 0

• Write remainders in reverse order to get the converted result.

– For the odd part after “.”

• Multiply by b until the result is 0

Page 20

Convert from base 10 to base 2

Eg1: 6.625(10) = ?(2)

– The integer part

Eg2: 20.75(10) = ?(2)

01

211

230

26

– The odd part after “.”

• 0.625 x 2 = 1.25

• 0.25 x 2 = 0.5

• 0.5 x 2 = 1.0

6.625(10) = 110.101(2)

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20.75(10) = ?(2) 10100.11(2)

20 2 0.75 * 2 = 1.5

0 10 2 0.5 * 2 = 1.0

0 5 2

1 2 2

0 1 2

1 0

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20.75(10)=?(8) =10100.11(2) = 24.6(8)

20 8 0.75 * 8 = 6.0

4 2 8

2 0

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Convert from base 2 to base 2n

Group from right to left n-bit groups and replace the equivalent values in base 2n

Eg:

101011(2) = ?(8) 1010.110(2)=12.6(8)

101011(2) = ?(16) 1010.110(2)=A.C(16)

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Convert from base 2n to base 2

Each digit in base 2n is replaced by n bit in base 2.

Eg:

37A.B(16)=?(2) = 0011 0111 1010 . 1011(2)

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Convert from base i to base j

If both i and j are powers of 2, use base 2 as an intermediate base:

– Eg: base 8 → base 2 → base 16

– 735.37(8)= 000111011101.01111100(2) = 1DD.7C ?(16)

Else, use base 10 as an intermediate base:

– Eg: base 5 → base 10 → base 2

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1.1.6 Other Codes

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Binary long addition similar to decimal long addition.

decimal binarycarry 110 11110

A 2565 10110

B 6754 11011

sum 9319 110001

Eg: 10101(2) + 11011(2) = 110000 ? (2)

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Overflow:

– Occur when the result of addition is out of range of representation (the result can not be stored in the predefined number of bits)

– In 8-bit computer, the result of addition of two binary numbers 10101010 and 11010011 is 9-bit binary number which can not be stored in 8-bit => overflow

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n-bit adder in computer:

A = an-1an-2...a1a0

B = bn-1bn-2...b1b0

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1.1.6 Other Codes

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Represent sign and amplitude

Use the most-left-bit to represent sign:

– 0: positive, 1: negative

Eg: represent signed numbers using 4 bit:

– +5 = 0101, -5 = 1101, -3 = 1011

– Using 3 right bits to represent amplitude, we can represent from -7 to +7.

– Drawbacks:

• +0 = 0000, -0 = 1000 => complex when calculating

=> need an other representation

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2’s complement representation

Most left bit is still sign bit

Positive and 0 numbers are expressed in usual binary format.

– The largest number can be represented is 2n-1-1

– n=8 => largest signed number: 28-1-1 = 127

Negative number a is stored as the binary equivalent of 2n-a in a n-bit system.

– -3 is stored as 28-3=11111101 in a 8-bit system

– The most negative number can be stored is -2n-1

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+10 = 0000 1010

- 10 = 28-10 = 1 0000 0000

– 0000 1010

1111 0110

- 10 = 1111 0110

+10 + (-10) = ? 0000 1010

1111 0110

1 0000 0000

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Procedure to find binary representation of negative number in 2’s complement:– Find the binary equivalent of the magnitude

– Complement each bit (0=>1, 1=>0)

– Add 1

Eg: find representation of -13 in 8-bit signed number system using 2’s complement:

• Magnitude: 13 = 0000 1101

• Complement: 1111 0010

• Add 1: 1

• -13 = 1111 0011+

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Range of representation:

– Use n bit to represent 2’s complement numbers

– Range: -2n-1 => 2n-1-1

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4 bit representation of unsigned and signed (2’s complement)

-1151111

-2141110

-3131101

-4121100

-5111011

-6101010

-791001

-881000

+770111

+660110

+550101

+440100

+330011

+220010

+110001

000000

SignedUnsignedBinary format

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To find the magnitude of a negative number:

– Complement each bit

– Add 1

Eg: 1001 0110(2) = -106?

0110 1001

+ 1

01101010 = 106

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Addition of signed numbers

The reason that 2’s complement is so popular is the simplicity of addition.

To add any two numbers, no matter what the sign of each is, we just do binary addition on their representation.

-2 1110 0 0000+2 0010

+3 0011+5 0101+7 0111

-5 1011-5 1011-5 1011

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Addition of signed numbers

Overflow

– Occur when?

– Add two numbers of the opposite sign?

– Add two positive numbers?

– Add two negative numbers?

maybe

⇒Overflow occurs when adding two numbers with the same sign and the result is in different sign

0110 0101 = 101 + 0101 0010 = 82 1011 0111

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1.1.6 Other Codes

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Find the 2’s complement of the second operand, then add.

a – b = a + (-b)

Eg: 7 – 5 = ?

-5 1011

2 0010 + 1

-5 +1011 1010

7 0111 5 0101

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1.1.6 Other Codes

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Binary-Coded Decimal - BCD

BCD:

– Use four bits (a nibble) to represent each of the decimal digits 0 through 9.

– Eg:

375 = 0011 0111 0101(BCD)

0001 0101111115

0001 0100111014

0001 0011110113

0001 0010110012

0001 0001101111

0001 0000101010

100110019

100010008

011101117

011001106

010101015

010001004

001100113

001000102

000100011

000000000

BCDBinaryDecimal

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1.1.6 Other Codes

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ASCII

American Standard Code for Information Interchange - ASCII

Use seven bits to represent various characters on the standard keyboard as well as a number of control signal

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Problems

1. Convert the following unsigned numbers:

98.625(10)=?(2)

11011.011(2)=?(10)

6A1.1E(16)=?(8)

2. Represent the following signed numbers:

a. -74 in 8-bit signed 2’s complement.

b. -74 in 16-bit signed 2’s complement.

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1. Introduction



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1.2.1 Definition of Switching Algebra

1.2.2 Basic Properties of Switching Algebra

1.2.3 Manipulation of Algebraic Functions

1.2.4 Representations of Algebraic Functions

1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

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Page 51


Switching algebra is binary:

– All variables and constant take on 0 or 1.

• Light on/off, switch: up/down, voltage: low/high...

– Quantities which are not naturally binary must be coded into binary format.

– Three operators:

• OR: a+b

• AND: a.b

• NOT: a’

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Page 53

Basic Properties of Switching Algebra

P1: Commutative:

• a + b = b + a a.b = b.a

P2: Associative:

• a + (b + c) = (a + b) + c a.(b.c) = (a.b).c

P3:

• a + 0 = a a . 1 = a

P4:

• a + 1 = 1 a . 0 = 0

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P5:

• a + a’ = 1 a . a’ = 0

P6: no coefficient and no exponent

• a + a = a a . a = a

• n.a=a (a)n=a

P7: complement

• (a’)’ = a

P8: distributive:

• a.(b+c) = a.b + a.c a + b.c = (a+b).(a+c)

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P9: adjacency

• ab + ab’ = a (a+b)(a+b’)=a

P10:

• a + a’b = a +b a(a’+b) = ab

P11: De Morgan

• (a + b)’ = a’b’ (ab)’ = a’ + b’

P12: absorption

• a + ab = a a(a+b) = a



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P13: redundant

• ab+b’c+ac = ab+b’c

A B

C


Page 57

Problems

1. Prove the following equalities:

a. xy’+y=x+y

b. xy+xz’+yz=xy+x’z => prove it incorrect

c. x’y’z+yz+xz=z

d. (x+y)[x’(y’+z’)]’+x’y’+x’z’ = 1

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Page 59

Manipulation of Algebraic Functions

A literal:

– Is the appearance of a variable or its complement

– Eg: x and x’ are two different literals

– Expression ab’+bc’d+a’d+e’ has 8 literals

A product term:

– Is one or more literal connected by AND operators

– Expression ab’+bc’d+a’d+e’has 4 product terms

– Note: A single literal is also a product term

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A standard product term - minterm:

– Is a product term which includes every variable of the function, either uncomplemented or complemented.

– Eg: for a function of four variables a,b,c,d:

• the product term a’bc’d is a standard product term

• the product term a’bd’ is not



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A sum of product - SOP:

– Is one or more product terms connected by OR operators

– Eg: ab’c+abc’+a’c+a’

» d

A canonical sum – sum of standard product term

– Is a sum of products expression where all terms are standard product terms.

– Eg: A function of three variables a,b,c:

• ab’c + abc’ + abc is a canonical sum

• ab’c + abc’ + a is not



Page 62

A minimum sum of products:

– Is one of those SOP expression for a function that has the fewest number of product terms.

– If there is more than one expression with fewest number of terms, then minimum is defined as one or more of those expressions with the fewest number of literals.

– Eg:

• F1(x,y,z) = x’yz’+x’yz+ xy’z’+xy’z+xyz

• F2(x,y,z) = x’y+xy’+xyz

• F3(x,y,z) = x’y+xy’+xz

• F4(x,y,z) = x’y+xy’+yz


F3,F4 are minimum SOP of F1


Page 63

A sum term:

– Is one or more literals connected by OR operators

– Eg:

• a + b’ + c’

• b’

A standard sum term - maxterm:

– Is a sum term that includes each variable of the problem, either uncomplemented or complemented

– Eg: For a function of four variables x,y,z,t

• x+y+z’+t’ is a maxterm

• x+y+t’ is not



Page 64

A product of sum – POS:

– Is one or more sum terms connected by AND

– Eg:

• (w+x’+y’)(w+y+z’)(w+x+z)

• w

A canonical product – product of standard sum terms:

– Is a product of sum term where all sum terms are standard



Page 65

A minimum POS is defined the same way as SOP:

– fewest number of terms

– the same number of terms => fewest number of literals



Page 66

Canonical forms

Three-variable minterm and Maxterm

x'+y’+z’ (M7)xyz (m7)1117

x'+y’+z (M6)xyz' (m6)0116

x'+y+z’ (M5)xy'z (m5)1015

x’+y+z (M4)xy’z’ (m4)0014

x+y’+z’ (M3)x'yz (m3)1103

x+y’+z (M2)x'yz’ (m2)0102

x+y+z’ (M1)x’y’z (m1)1001

x+y+z (M0)x’y’z’ (m0)0000

MaxtermmintermzyxDecimal

Page 67

Canonical forms

Properties of minterm/Maxterm:

– mimj=0 if i≠j

=mi if i=j

– Mi+Mj=1 if i≠j

= Mi if i=j

– mi=Mi’ and Mi=mi’ for every i

Page 68

Canonical forms

An algebraic expression of a Boolean function can be derived from a given truth table in two ways:

– By summing (ORing) those minterm for which the function takes a value 1.

– By multiplying (ANDing) those maxterm for which the function takes a value 0.

Page 69

Canonical forms

11117

10116

11015

10014

01103

00102

11001

00000

fx0x1x2Decimalf(x2,x1,x0)=m1+m4+m5+m6+m7

=Σ(1,4,5,6,7)

f(x2,x1,x0)=M0M2M3

= Π(0,2,3)

Canonical sum-of-products (SOP)

Canonical product-of-sums (POS)

Page 70

F(a,b,c)= abc’+a’b’

F(a,b,c)=m0+m1+m6

– ∑(0,1,6)

01117

10116

01015

00014

01103

00102

11001

10000

fcbaDecimal

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Page 72


Truth table

Venn diagram

Karnaugh map

Page 73

Truth table

List all the possible binary combinations of the independent variables and display the corresponding binary values of dependant variables.

Page 74

Truth table

n independent variables and m dependant functions:

2n rows

n+m columns 3 independent variables

2 dependent functions

23 rows

Page 75

Venn diagram

Venn diagram using ‘space’ to present logic

F(A,B)=A.B

A B

C

F(A,B,C)=C.not(B)

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Venn diagram

A A

A+B A.B

A.B A+B

Page 77

Karnaugh map

67541

23100

10110100

BC

A

5410

7611

3201

1000

10

C

AB

A Karnaugh map is a graphical method for representing the true table of a Boolean function.

K-map may be used for any variables number, but often at most six.

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Karnaugh map (K-map)

If variables number is n => 2n cells in K-map.

2n cells are arranged in logical pattern for minimization purpose.

67541

23100

10110100

BC

A

Page 79

Two-variable K-map

F(A,B)

3

2

1 0

AB 0 1

0

1

3 1

2 0

BA 0 1

0

1

Page 80

Two-variable K-map

F(A,B) = AB

10

00

AB 0 1

0

1

Page 81

Three-variable K-map

F(A,B,C)

67541

23100

10110100

BC

A

5410

7611

3201

1000

10

C

AB

Page 82

Three-variable K-map

F(x,y,z) = xyz + yz’ + x

1111

1011

1101

1001

0110

1010

0100

0000

Fzyx

11111

10000

10110100

yz

x

1110

1111

0101

0000

10

z

xy

Page 83

Four-variable K-map

10

11

01

00

10110100CD

AB

F(A,B,C,D)

Page 84

Four-variable K-map

F(A,B,C,D) = AB + CD’ + BCD

100010

111111

110001

100000

10110100CD

AB

Page 85

Five-variable K-map

00 01 11 10ABCD

00011110

00 01 11 10ABCD

00011110

E 0 1

5 variables Karnaugh Map consists of two4 variables Karnaugh Map connected up/down.

Page 86

Six-variable K-map

1 1 1 1 1 1

00 01 11 10ABCD

00011110

1 1 1 1 1 1

00 01 11 10ABCD

00011110

E 0 1

1 1 1 1 1 1

00 01 11 10ABCD

00011110

1 1 1 1 1 1

00 01 11 10ABCD

00011110

F

0

1

Page 87

Karnaugh map with don’t care

CD00 01 11 10

00

01

11

10

AB

1 1

1 1

− − − −

− −

don’t care ~ input conditions that not occur

Page 88







Page 89

Basic logic gates

AND OR NOT

111

001

010

000

outBA

111

101

110

000

outBA

01

10

outA

http://en.wikipedia.org/wiki/Image:Or-gate.png

Page 90

Basic logic gates

NAND NOR XOR

011

101

110

100

outBA

011

001

010

100

outBA

011

101

110

000

outBA

Page 91

Implementation of Functions with AND, OR

Assume all inputs are available in uncomplemented and complemented

F1 = x’yz’+x’yz+xy’z’+xy’z+xyz

F2 = x’y+xy’+xz

Page 92

Implementation of Functions with AND, OR, NOT

Complemented inputs can be produced using inverters NOT:

X

Y

Z

F

Page 93

Multilevel circuits

A circuit is called n-level circuit if the maximum number of gates through which one signal must pass from input to output

two-level circuit three-level circuit

Page 94

Implementation of Functions with NAND

Using equivalent change steps, every expression can be represented using only NAND gates.

NOT

AND

OR

A

B

A.B (A’.B’)’=A+B

A

B

Page 95

Implementation of Functions with NAND

Represent the following expression using only NAND:

– F(a,b,c) = ab + bc’ + b’

=

bcbabbcbabbcbab ..=++=++

Page 96

Implementation of Functions with NOR

Using equivalent change steps, every expression can be represented using only NOR gates.

U10A

7402N

U11A

7402N

U7A

7402N

U8A

7402NU9A

7402N

A

B

( A' +B' ) ' =A. BA'

B'U3A

7402N

A

( A+A) ' =A'

Page 97

Implementation of Functions with NOR

Represent the following expression using only NOR:

– F(a,b,c) = ab + bc’ + b’

Page 98

Chapter 2.

Logic Function Minimization Methods

Page 99


2.1 Algebraic Method

2.2 The Karnaugh Map Method

2.3 Quine-McCluskey Method

Page 100

What is minimization?

– Number of operands is minimal and number of literal in each operand is minimal

Why minimization needed?

– Minimize electronic components used to construct the circuit to implement that expression


Page 101





Page 102

2.1. Algebraic Method

Use algebraic properties to minimize expressions

Drawback:

– Heuristic, depending on experience – no formal method/procedure

– Manually

– Not sure whether the last expression is minimal or not

Page 103

2.1. Algebraic Method

Eg: Minimize these expressions using algebraic method:

– F0(x,y,z)=xyz+x’yz+xy’z+xyz’

– F1(a,b,c,d)=ab+abc+a’cd+a’c’d+a’bcd’

– F2(A,B,C,D)=

– F3(x,y,z)=(x+y)(x+y+z’)+y’

– F4(a,b,c,d)=(a+b’+c)(a+c’)(a’+b’+c)(a+c+d)

))(.()( CADCBABCA ++++

Page 104





Page 105


1. Minimum Sum of Product Expressions Using the Karnaugh Map

2. Don’t Cares

3. Product of Sums

4. Minimum Cost Gate Implementation

5. Five- and Six-Variable Maps

6. Multiple Output Problems

Page 106

Implicant, Prime Implicant

An implicant of a function is a product term that can be used in a SOP

10

111111

101

1100

10110100

CD

AB Implicants of F

Minterm Groups of 2 Groups of 4A’B’C’D’ A’CD ABA’B’CD BCDA’BCD ABC’ABC’D’ ABDABCD’ ABCABC’D ABD’ABCD

Page 107

Implicant, Prime Implicant

A prime Implicant is an implicant which can not be contained in any other implicants.

111110

1111

1101

11100

10110100

CD

AB

B C

* B D

* B D

A D

A B

C D

Page 108

Essential Prime Implicant

Essential PI is a PI which contains at least one minterm which is not contained in other PI.

111110

1111

1101

11100

10110100

CD

AB

B C

* B D

* B D

A D

A B

C D

minterm 0 is only contained in PI B’D’minterm 5 is only contained in PI BD=> BD & B’D’ are two Essential PI

Page 109

2.2.1 Minimum Sum of Product Expressions

Rules to minimize using K-map:

– Rule 1: Fill K-map cells with corresponding values

– Rule 2: Group adjacent cells whose values are 1. Number of cells is 2n.

– Rule 3: Each group will be a part of result. Variables in each group will be excluded: 2n cells => exclude n variables.

Page 110


Step 2: Group adjacent cells whose values are 1. Number of cells is 2n.

1110

1111

1101

00

10110100

CD

AB

1110

1111

1101

1100

10110100

CD

AB

Page 111

Step 3: Each group will be a part of result. Variables in each group will be excluded: 2n cells => exclude n variables.

1110

1111

1101

00

10110100

CD

AB

21 cells => eliminate 1 variable

22 cells => eliminate 2 variables

F(A,B,C,D) = A’BC’ + AC


Page 112

Example 1: Minimize these functions using K-map:

– a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)

– b. F(A,B,C,D) = R(1,3,5,8,9,13,14,15)

– c. F(A,B,C,D) = R(2,4,5,6,7,9,12,13)

– d. F(A,B,C,D)= R(1,3,4,5,7,9,13,14,15)

– e. F(A,B,C,D)=R(1,3,4,6,9,11,12,14)


Page 113

– a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)

= BC’D + AB’D + BCD’ + A’B’D’

1110

11

11

1101

1100

10110100

CD

AB

Page 114

– b. F(A,B,C,D) = R(1,3,4,6,9,11,12,14)

= B’D + BD’

1110

11

11

1101

11

00

10110100

CD

AB

Page 115

2.2 The Karnaugh Map

1. Minimum Sum of Product Expressions Using the Karnaugh Map

2. Don’t Cares

3. Product of Sums

4. Minimum Cost Gate Implementation

5. Five- and Six-Variable Maps

6. Multiple Output Problems

Page 116

2.2.2 Don’t care

If the function has don’t care values in cells:

– Cells with don’t care values

can be grouped with ‘1’ cells

– Do not group only don’t

care cells in one group.

CD00 01 11 10

00

01

11

10

AB

1 1

1 1

− − − −

− −

CBCBDCBAF +=),,,(

Page 117

Examples:

F(a,b,c,d)=R(1,3,5,7,12,13)don’t care (0,4,10,15)

-10

-1111

11-01

11-00

10110100

CD

AB

Page 118





Page 119


1. Quine-McCluskey Method for One Output

2. Iterated Consensus for One Output

3. Prime Implicant Tables for One Output

4. Quine-McCluskey for Multiple Output Problems

5. Iterated Consensus for Multiple Output Problems

6. Prime Implicant Tables for Multiple Output Problems

Page 120

2.3. Quine-Mcluskey method

Karnaugh map cannot handle more than 6 variables. Quine-McCluskey method has no limitation with number ofvariables, and is suitable for computer algorithm.

0 100 01 111 1 110 1 1

ABC

ABC+ABC+ABC+ABC+ABC

010

*10 11* 1*0 1*1 10*

110 111 100 101

1**

find a pair of numbers of 1 bit difference

Page 121

Quine-Mcluskey Procedure

1: Represent minterms in binary numbers

2: Group each minterm by the number of ‘1’ appearance

3: Make set of 1 bit different numbers between neighboring group

• write the difference within parenthesis

• mark * to the number which is not included in a set

4: Make set of 1 bit different sets with the same number in a parenthesis

• append the difference to parenthesis

• mark + to the set which is not included in a set

5: Iterate these step until all the generated set is marked *

6: Select prime implicants

7: Convert to logic variable

Page 122

S1. Represent minterms in binary numbers

f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF +ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF

f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010

f(A,B,C,D,E,F)=Σ(0,2,6,7,14,8,41,12,15,10)

Page 123

S2. Grouping

f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010

000000

once twice three times

000010001000

000110001100001010

000111001110101001

four times

001111

group 0 group 1 group 2 group 3 group 4

group each term by the appearance of 1

no times

Page 124

S3 & S4. Making set (1)

000000 0 000010 2001000 8

000110 6001010 10001100 12

000111 7001110 14101001 41

001111 15

0,2 (2)0,8 (8)

2,6(4)2,10(8)8,10(2)8,12(4)

6,7(1)6,14(8)10,14(4)12,14(2)

7,15(8)14,15(1)

find a pair of 1 bit differencebetween neighboring groupwrite difference within ( )

mark to the number not included in any set

group 0

group 1

group 2

group 3

group 4

Page 125

S3 & S4. Making set (2)

0,2 (2)0,8 (8)

2,6(4)2,10(8)8,10(2)8,12(4)

6,7(1)6,14(8)10,14(4)12,14(2)

7,15(8)14,15(1)

0,2,8,10(2,8)

2,6,10,14(4,8)8,10,12,14(2,4)

6,7,14,15(1,8)

mark to the setnot involvedin the next level set

when all the set is markedfinish

Each pair appears in duplicate

find a pair of 1 bit different setswith the same value in ( )between neighboring groupappend difference within ( )

Page 126

S6. Selecting Prime Implicants (1)

410,2,8,10(2,8)2,6,10,14(4,8)8,10,12,14(2,4)6,7,14,15(1,8)

0 2 6 7 8 10 12 14 15 41

x x x xx

x x x xx x x x

x x x x

If only one x in a column, then the row is inevitable implicant

minterms (given at first)

Prim

e implicant

（　m

arked

）

write x into the position where minterm is includedin the prime implicant

inevitableimplicant

Page 127

S6. Selecting Prime Implicants (2)

410,2,8,10(2,8)2,6,10,14(4,8)8,10,12,14(2,4)6,7,14,15(1,8)

0 2 6 7 8 10 12 14 15 41

x x x xx

x x x xx x x x

x x x x

mini term

prime im

plicants

mark minterms involved in theinevitable implicants inevitable

implicants

Page 128

S7. Conversion to logic variables

41 101001

0,2,8,10(2,8)

000000000010001000001010

8,10,12,14(2,4)001000001010001100001110

6,7,14,15(1,8)000110000111001110001111

ABCDEF

ABDF

ABCF

ABDE

F=ABCDEF +ABDF +ABCF +ABDE

Page 129

Examples:

Minimize the following functions using Quine-Mcluskey method:

– a.

– b. F(a,b,c,d,e,f) =

∑(17,21,25,29, 44,45,46,47,49,52,53,54,55,47,61)

fedbafdcbfebcaefdba +++=f)e,d,c,b,F(a,

Page 130

Quine-Mcluskey method with don’t care

1: Represent logic function in sum of mini terms ==>A

2: Represent don’t care in sum of mini terms ==>B

3: If there exist duplication in A and B, remove from A

4: Apply Quine-McCluskey method for A and B

5: Be careful not to include B in selecting prime implicants

Page 131


f=ABCD+BCD+ACD+ABCD+ABCDdon’t care AD

mini termABCD

000000010010001101010111101111011111

decimal

0 1 2 3 5 7111315

first comparison second comparison0,1(1)0,2(2)1,3(2)1,5(4)2,3(1)3,7(4)3,11(8)5,7(2)5,13(8)7,15(8)11,15(4)13,15(2)

0,1,2,3(1,2)

1,3,5,7(2,4)

3,7,11,15(4,8)5,7,13,15(2,8)

Page 132


0 2 11 13 150,1,2,3(1,2)

1,3,5,7(2,4)3,7,11,15(4,8)5,7,13,15(2,8)

xx

xxx

x

00**0**1**11*1*1

ABCD

f=AB+CD+BD

Page 133

Chapter 3.

Larger Combinational Systems

Page 134

Introduction

Logic circuits are divided into two classes:

– Combinational logic circuits

• Output signals only depend on current input signals

• Memoryless circuits

– Sequential logic circuits

• Output signals not only depend on current input signals, but also depend on those input signals in the past

• Memory circuits

Page 135


3.1 Delay in Combinational Logic Circuits

3.2 Adders and Other Arithmetic Circuits

3.3 Decoders

3.4 Encoders

3.5 Multiplexers

3.6 Demultiplexers

3.7 Three-State Gates

3.8 Gate Arrays-ROMs, PLAs and PALs

3.9 Larger Examples

Page 136


Delay through logic gates

– When the input to a gate changes, the output of that gate doesn’t change immediately; but there is a small delay Δ.

– The output is stable after the longest delay path

A

B

CF

X

Page 137



3.3 Decoders

3.4 Encoders

3.5 Multiplexers

3.6 Demultiplexers



3.9 Larger Examples


Page 138

Half Adder

a b Σ r

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Σ=a ⊕ b

r = ab

=1

&

a

b

Σ

r

Half Adder

HAa

b

Σr

(Result)

(Carry-out)

Page 139

Addition of two n-bit numbers

Σ4 Σ3 Σ2 Σ1 Σ0

r3 r2 r1 r0

A = a3 a2 a1 a0

+B = b3 b2 b1 b0

r4 Σ3 r3 Σ2 r2 Σ1 r1 Σ0

Summation

Page 140

Full Adder

FAai

ri

bi

Σ i

ri+1

ai bi ri Σ iri+1

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

111

110

10110100 aibi

ri

Σ i

1111

10

10110100 aibi

ri

ri+1

Σi = ai ⊕ bi ⊕ ri

ri+1 = ai bi + ri (ai ⊕ bi)

Page 141

Combinational logic circuit design procedure

Problems: design a combinational logic circuit to do smth.

Design procedure:

– S1: Find inputs, outputs and relations.

– S2: Construct truth table

– S3: For each output, using K-map to minimize from truth table.

– S4: Draw the circuit.

Page 142

Example 1

Problem: Design a combinational logic circuit to implement this operation: M=N+3, N is 3-bit binary number, the number of bit of M is selected properly.

Solution:

– S1: three inputs: n2n1n0

four outputs: m3m2m1m0

Page 143

Example 1

S1: three inputs: n2n1n0

four outputs: m3m2m1m0

S2: truth table

0101111

1001011

0001101

1110001

0110110

1010010

0010100

1100000

m0m1m2m3n0n1n2

S3:

11101

00000

10110100 n1n0

n2

m3 = n2n0 + n2n1

n2n1n0

m3m2m1m0

Page 144

Example 2

Problem: design a combinational logic circuit to calculate square of a 2-bit binary number.

Solution:

– Step1: find inputs, outputs

• Inputs: a1,a0

• Outputs: b3,b2,b1,b0

Ex2

Page 145

– Step 2: truth table

– Step3: using K-map to minimize outputs

• b3 = a1.a0 b1 = 0

• b2 = a1.a0’ b0 = a0

Example 2

100111

001001

100010

000000

b0b1b2b3a0a1

Page 146

Example 2

– Step 4: Draw circuit

• b3 = a1.a0 b1 = 0

• b2 = a1.a0’ b0 = a0

a1

a0

b3

b2

b1

b0

U1A

7408N

U1B

7408N

U2A

7404N

X1

2.5 V X2

2.5 V X3

2.5 V X4

2.5 V

R1100

V15 V

J1

Key = A

R2100

V212 V

J2

Key = B

Page 147

Full Adder

=1

&

ri

ai

bi

=1

&

Σ i

ri+1

≥1

Page 148

Full Adder

=1

&

ri

ai

bi

=1

&

Σ i

ri+1

≥1

HA HA

Page 149

n-bit Adder

Serial n-bit adder

A = an-1an-2...a1a0 , B = bn-1bn-2...b1b0

FA

an-1 bn-1

rn-1

rn

Σn-1

FA

an-2 bn-2

rn-2

Σn-2

FA

a1 b1

r1

r2

Σ1

FA

a0 b0

r0= 0

Σ0Σn

Delay = n x Δ?

Page 150

n-bit Adder

Parallel n-bit adder:

ri+1 = aibi + ri(ai ⊕ bi) Pi = ai ⊕ bi and Gi = aibi → ri+1 = Gi + ri Pi

r1 = G0 + r0P0

&

≥ 1G0

P0

r0

r1

τ1 τ2

r2 = G1 + G0P1 + r0P0P1

&

≥ 1G1

G0

P1

r2

τ1τ2

&P0

r0

Page 151

Parallel 4-bit addition

r4 = Σ4 Σ3 Σ2 Σ1 Σ0

r2 r1 a2 b2 a1 b1

a0 b0

P3 G3 P2 G2 P1 G1 P0 G0

Calculate Pi and Gi

a3 b3 a2 b2 a1 b1 a0 b0

Carry calculation

Sum calculation

r0 a3 b3

r3 r4

r0

Page 152

Subtractor

To subtract a-b, simply add a to 2’s complement of b.

Second choice:

Half Subtractor => Full Subtractor => n-bit Subtractor

Page 153

Subtractor

Subtractor by using 2’s complement

A3 A2 A1 A0

B3 B2 B1 B0

S3 S2 S1 S0

1C1C2C3

C4A B

C

S

C+ FAA B

C

S

C+ FAA B

C

S

C+ FAA B

C

S

C+ FA

Page 154

Adder and Subtractor

C1C2C3C4

A B

C

S

C+ FAA B

C

S

C+ FAA B

C

S

C+ FAA B

C

S

C+ FA

MPX MPX MPX MPX

A3 A2 A1 A0B3 B2 B1 B0

S3 S2 S1 S0

sel

Page 155




3.3 Decoders

3.4 Encoders

3.5 Multiplexers

3.6 Demultiplexers



3.9 Larger Examples

Page 156

Decoder

An nxm decoder is a combinational circuit that converts binary information from n input lines to m output lines, where m≤2n.

– m = 2n => complete decoder

Fundamental property: only one output is 1 for any given input combination.

Page 157

Decoder

Complete decoders: m=2n

Eg: + 3 bit inputs x1,x2,x3. + 8 bit outputs Y0,Y1…Y7

nxm decoder

.

.

.

.

.

.

x1

x2

xn

D0

D1

Dm-1

E

3x8 decoder ...

x1

x2

x3

D0

D1

D7

Page 158

Design 3x8 decoder

3x8 decoder ...

x1

x2

x3

D0

D1

D7

En

if (En=0)Disable or D0...D7=0

else if (En=1)Function as a 3x8 decoder

Page 159

BCD-to-decimal decoder

BCDto

decimalDecoder

ABCD

Y0

Y1

Yi

Y9

:

:

N A B C D Y0 Y1 ..

Y9

0 0 0 0 0 1 0 ..

0

1 0 0 0 1 0 1 ..

0

2 0 0 1 0 0 0 ..

0

3 0 0 1 1 0 0 ..

0

4 0 1 0 0 0 0 ..

0

5 0 1 0 1 0 0 ..

0

6 0 1 1 0 0 0 ..

0

7 0 1 1 1 0 0 ..

0

8 1 0 0 0 0 0 ..

0

9 1 0 0 1 0 0 . 1

Page 160

BCD-to-decimal decoder

0 1Y A B C D Y A B C D

2Y BCD

3

4

5

6

7

8

9

Y BCD

Y BC D

Y BC D

Y BC D

Y BCD

Y AD

Y AD

− −10

− − − −11

01

100

10110100 CD

AB

Page 161

Decoder

4x16 decoder using two 3x8 decoders

3x8 decoder ...

x2

x3

x4

D0

D1

D7

3x8 decoder ...

x1

D8

D9

D15

Page 162

Decoder implementation of arbitrary functions

4x16 decoder

x2

x3

x4

D0

D1

D2

x1

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13D14

D15

F1

F1(x1,x2,x3,x4)=Σ(0,1,3,8,12)

Page 163

BCD-to-7segment decoder

a

b

c

d

e

f g

Each segment is a LightEmitting Diode (LED)

KA

110111110019

111111100018

000011111107

111110101106

110110110105

110011000104

100111111003

101101101002

000011010001

011111100000

gfedcbaDCBAN

Page 164

BCD-to-7segment decoder

− −1110

− − − −11

111001

110100

10110100

CD

AB

a A C BD B D

&

&

B

D

≥ 1A

C

Page 165



3.3 Decoders

3.4 Encoders

3.5 Multiplexers

3.6 Demultiplexers



3.9 Larger Examples


Page 166

Encoder

An encoder is a circuit that performs the function of a decoder in reverse.

An mxn encoder has m inputs, n outputs where m≤2n. The outputs generate the binary codes corresponding to m inputs.

For example: encoder for PC’s keyboard

Key <=> Character <=> Key code

102 keys, 8 bit ASCII

Page 167

Keyboard encoder

9 keys

4-bit key code.

1

2

i Encoder

9

P2

P1

Pi

A

B

C

D

N=i

‘1’

P9

Page 168

Keyboard encoder

A = 1 if (N=8) or (N=9)B = 1 if (N=4) or (N=5) or (N=6)

or (N=7)C = 1 if (N=2) or (N=3) or (N=6)

or (N=7)D = 1 if (N=1) or (N=3) or (N=5) or (N=7) or (N=9)

10019

10008

01117

01106

01015

01004

00113

00102

00011

ABCDN

Page 169

Keyboard encoder

≥ 1

≥ 1

≥ 1

≥ 1

N=9

N=8

N=7

N=6

N=5

N=4

N=3

N=2

N=1

A

B

C

D

Page 170



3.3 Decoders

3.4 Encoders

3.5 Multiplexors

3.6 Demultiplexors



3.9 Larger Examples


Page 171

Multiplexor

Multiplexor has one output and more than one input.

Function: select one of input for output

X0

X1

C0

Y

MUX 2-1

C0 Y

0 X0

1 X1

C1 C0 Y

0 0 X0

0 1 X1

1 0 X2

1 1 X3

control inputs

X0

X1

X2

X3

C0

C1

Y

MUX 4-1

Page 172

2-to-1 Multiplexor

X0

X1

C0

Y

MUX 2-1

C0 Y

0 X0

1 X1

0 0 1 0Y X C X C111

110

10110100 X1X0

C0

C0 X1 X0 Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

Page 173

2-to-1 Multiplexor

Page 174

4-to-1 Multiplexor

Y = s1’s0’I0 + s1’s0I1 +s1s0’I2+ s1s0I3

Page 175

Application of multiplexor

Select source

Source 1 Source 2

Receiver

Y3 Y2 Y1 Y0

A = a3 a2 a1 a0 B = b3 b2 b1 b0

C0

Page 176


Convert parallel-serial

a0

a1

a2

a3

C0

C1

Y

a0 a1 a2 a3

Y

C1

C0

0

1

0

1

t

t

t

A

Page 177


Implementation of arbitrary functions:

f(A,B) A Bf(0,0) A Bf(0,1) A Bf(1,0) A Bf(1,1)

1 0 0 1 0 1 1 0 2 1 0 3Y C C X C C X C C X C C X

x0

x1

x2

x3

C1 C0

f(0,0)

f(0,1)

f(1,0)

f(1,1)

A

B

Y = f(A,B)Inputs to select function

Variables

Page 178

Example

F(A,B) = A’B + AB’

x0

x1

x2

x3

C1 C0

0

1

1

0

A

B

Y = f(A,B)Inputs to select function

Variables

Page 179




3.3 Decoders

3.4 Encoders and Priority Encoders

3.5 Multiplexers

3.6 Demultiplexers



3.9 Larger Examples

Page 180

Demultiplexor

Demultiplexor has one input and more than one output

Function: select one of outputs for input

E

C0

S0

S1

ECS

ECS

01

00

==

DeMUX 1-2

Page 181

Demultiplexor 1-4

E

C1

C0

S0

S1

S2

S3

Page 182



3.3 Decoders


3.5 Multiplexers

3.6 Demultiplexers



3.9 Larger Examples


Page 183

3.7 Three-State Gates (Tristate)

Three state gates exhibit three states instead of two states. The three states are:

– High : 1

– Low : 0

– High impedance : z

• In this state the output is disconnected which is equal to open circuit. In the other words in that state circuit has no logic significant. We can have AND or NAND three-state gates but the most common is three-state buffer gate

Page 184

3.7 Three-State Gates (Tristate)

We may use conventional gates such as AND or NAND as three-state gates but the most common is three-state buffer gate.

Note that buffer produces transfer function and can be used for power amplification. Three state buffer has extra input control line entering the bottom of the gate symbol (see next slide)

Page 185

Three-State buffer

Three-state buffer

C A Y----------------------0 0 z0 1 z7 0 01 1 1

Page 186

Application of three-state buffer

Three-state buffers can be used to implement

multiplexer

Page 187




3.3 Decoders


3.5 Multiplexers

3.6 Demultiplexers


3.8 Gate Arrays - ROMs, PLAs and PALs

3.9 Larger Examples

Page 188

3.8 Gate Arrays - ROM, PLA and PAL

PLA - Programmable Logic Arrays

PAL - Programmable Array Logic

ROM

Page 189

PLA - Programmable logic arrays

Pre-fabricated building block of many AND/OR gates

– actually NOR or NAND

– "personalized" by making or breaking connections among the gates

– programmable array block diagram for sum of products form

• • •

inputs

ANDarray

• • •

outputs

ORarrayproduct

terms

A B C Z1 Z2m0 0 0 0 0 1m1 0 0 1 0 0m2 0 1 0 1 1m3 0 1 1 0 0m4 1 0 0 0 1m5 1 0 1 1 0m6 1 1 0 1 1m7 1 1 1 1 0

Page 190

Before programming

All possible connections are available before "programming"

– in reality, all AND and OR gates are NANDs

Page 191

After programming

Unwanted connections are "blown"

– fuse (normally connected, break unwanted ones)

– anti-fuse (normally disconnected, make wanted connections)

A B C

F1 F2 F3F0

AB

B'C

AC'

B'C'

A

Page 192

PLA example

Multiple functions of A, B, C

– F1 = A B C

– F2 = A + B + C

– F3 = A' B' C'

– F4 = A' + B' + C'

– F5 = A xor B xor C

– F6 = A xnor B xnor C

A B C F1F2F3F4F5 F60 0 0 0 0 1 1 0 00 0 1 0 1 0 1 1 10 1 0 0 1 0 1 1 10 1 1 0 1 0 1 0 01 0 0 0 1 0 1 1 11 0 1 0 1 0 1 0 01 1 0 0 1 0 1 0 01 1 1 1 1 0 0 1 1

A'B'C'

A'B'C

A'BC'

A'BC

AB'C'

AB'C

ABC'

ABC

A B C

F1 F2 F3 F4 F5F6

full decoder as for memory address

bits stored in memory

Page 193

PALs and PLAs

Programmable logic array (PLA)

– what we've seen so far

– unconstrained fully-general AND and OR arrays

Programmable array logic (PAL)

– constrained topology of the OR array

– innovation by Monolithic Memories

– faster and smaller OR plane

a given column of the OR array has access to only a subset of

the possible product terms

Page 194

ROM – Read Only Memories

Two dimensional array of 1s and 0s

– entry (row) is called a "word"

– width of row = word-size

– index is called an "address"

– address is input

– selected word is output

decoder

0 n-1

Address

2 -1n

0

1 1 1 1

word[i] = 0011

word[j] = 1010

bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches)

j

i

internal organization

word lines (only one is active – decoder is just right for this)

Example:10 address x 8 data ROM210 words x 8 ROM 1024 words x 8 ROM1k x 8 ROM

Page 195

ROM – Read Only Memories

F0 = A' B' C + A B' C' + A B' C

F1 = A' B' C + A' B C' + A B C

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C'

truth table

A B C F0 F1 F2 F30 0 0 0 0 1 00 0 1 1 1 1 00 1 0 0 1 0 00 1 1 0 0 0 11 0 0 1 0 1 11 0 1 1 0 0 01 1 0 0 0 0 11 1 1 0 1 0 0 block diagram

ROM8 words x 4 bits/word

address outputsA B C F0 F1 F2 F3

Combinational logic implementation (two-level canonical form) using a ROM

Page 196

ROM structure

Similar to a PLA structure but with a fully decoded AND array

– completely flexible OR array (unlike PAL)

n address lines

• • •

inputs

decoder 2n wordlines

• • •

outputs

memoryarray

(2n wordsby m bits)

m data lines

Page 197




3.3 Decoders


3.5 Multiplexers

3.6 Demultiplexers



3.9 Larger Examples

Page 198

3.9 Larger Examples

1. Seven-segment displays

2. Comparator

Page 199

Comparator

1-bit full comparator:

1bit Full

Comparator

ai

bi

Gi

Li

Ei

iii

iii

iii

baE

baL

baG

⊕=

=

=

.

.ai > bi Gi=1ai < bi Li=1ai = bi Ei=1

Page 200

Comparator

N-bit parallel comparator:

Page 201

Midterm examination (90’)

1. Represent the following function in the canonical form SOP:

F(A,B,C)=(A+B’)C

2. Use the Quine-McCluskey method to obtain the minimal sum for the following function:

F(A,B,C,D,E)= ∑(1,4,6,7,8,9,10,11,15)

3. Design 4x16 decoder using only 2x4 decoders.

4. Design a combinational logic circuit to calculate the following function: M=N+3 where N is BCD number (Binary-Coded Decimal).

Page 202

Midterm examination 2 (90’)

1. Represent the following function in the canonical form SOP and POS:

F(A,B,C)=C

2. Use the Quine-McCluskey method to obtain the minimal sum for the following function:

F(A,B,C,D,E)= ∑(1,4,6,7,8,11,12,13,15)

3. Using 3x8 decoder to implement the following function:

F(A,B,C) = AB + B’C

4. Design a combinational logic circuit to calculate the following function: M=N+5 where N is BCD number (Binary-Coded Decimal).

Page 203

Chapter 4.

Sequential Systems

Page 204


4.1 Definitions

4.2 State Tables and Diagrams

4.3 Latches and Flip Flops

4.4 Analysis of Sequential Systems

4.5 Design of Sequential Systems

4.6 Solving Larger Sequential Problems

Page 205

4.1 Definitions

Combinatorial circuit is memoryless.

In a circuit with memory, an output value at tn+1 must be a function not only of the inputs at tn+1 but also of the outputs at tn.

To achieve this, the circuit must have some feedback connections from its outputs to its inputs.

A circuit with memory is a combinatorial circuit incorporating some feedback connections.

Page 206

Feedback and memory devices

To implement feedback, signals are fed back from outputs to inputs using memory devices.

A memory device stores an output value at time tn so that it can be input to the circuit at tn+1.

But then, output at tn depends on input at tn-1, which in turn depends on tn-2…

The circuit maps input sequences to output sequences

Page 207

Sequential circuit model

Circuits with memory are called sequential circuits.

Combinatorial circuit

.

..

x1

x2

xn

.

..

z1

z2

Memorydevice

Memorydevice

..

.

Yk

Y1

yk

y1

Circuit inputs Circuit outputs

Present state Next state

Page 208

Sequential circuit model

Mealy model:

• X : finite inputs. m inputs: x1,x2...,xm

• S : finite states. n states: s1,s2...,sn

• Y: finite outputs.l outputs: y1,y2...,yl

• Fs: state function. s = Fs(X,S)

• Fy : output function. y = Fy(X,S)

Moore: ~Mealy

• Difference: Fy = Fy(S)

Page 209

Asynchronous/Synchronous sequential circuits

The timing of the signal in the circuit determine two types of sequential circuits:

– Synchronous

– Asynchronous.

Page 210

Synchronous sequential circuits

In a synchronous sequential circuit, the state can change only at discrete instants of time.

To achieve that, the circuit uses a timing device, called a clock generator, that produce trains of periodic or aperiodic clock pulses.

The clock pulses are input to the memory devices so that they can change state only in response to the arrival of a pulse and only once for each pulse occurrence.

The operation of the circuit is synchronized with the clock pulse input.

Page 211

Asynchronous sequential circuits

The behavior of an asynchronous sequential circuit depends only on the order in which the inputs change and can be affected at any instant of time.

There is no timing device in asynchronous sequential circuit (unclocked memory).

Page 212


4.1 Definitions






Page 213

State diagram

Depict graphically the operation of a sequential circuit.

– Mealy state diagram

a b c d0/0 1/0 0/0

0/00/0

1/0 1/1

Page 214

Example of state diagram

A B C D0 / 0

1 / 0 0 / 0

1 / 0

1 / 0

0 / 0

0 / 0

1 / 1

Example: a sequential circuit is used to detect the string “0101” from one input.

Page 215

State diagram

Depict graphically the operation of a sequential circuit.

– Moore state diagram

a/0

b/0

c/0

d/0

e/1

f/1

01 0

0

0

0

0

1

1

1

1

1

Page 216

State table

State table presents in a tabular form the same information contained in the state diagram.

– Mealy state table

– Moore state table

Page 217

Mealy state table

10cbd

00adc

00cbb

00aba

x=1x=0x=1x=0

Output (z)NSPS

c/1b/0d

a/0d/0c

c/0b/0b

a/0b/0a

x=1x=0

NS/Output (z)PS

PS: Present StateNS: Next State

k memory devices => 2k rowsn circuit inputs => NS portion contains 2n columns Output portion also contains 2n columns

a b c d0/0 1/0 0/0

0/00/0

1/0 1/1

Page 218

Moore state table

1aff

1efe

0edd

0cdc

0cbb

0aba

zx=1x=0

OutputNSPS

The output portion always contains a single column.

The entry at the intersection of any row with the output column indicates the output values corresponding to the PS associated with that row.

a/0

b/0

c/0

d/0

e/1

f/1

01 0

0

0

0

0

1

1

1

1

1

Page 219

Incompletely specified Mealy state table

Two inputs: x1,x2

A single output: z

b/0c/1-/-c/0f

a/0d/1f/0-/-e

b/1e/--/-a/-d

-/--/-f/1f/0c

-/--/--/-e/0b

e/1b/-c/1-/-a

10110100

NS/Output (z)PS

Page 220


4.1 Definitions






Page 221

4.3. Latches and Flip-Flops

Simplest memory devices: Delay element

ΔTYi yi

yi(t+ΔT) = Yi(t)

ΔT

Yi

yi

In practice, we don’t have to actually insert delay elements because propagation time delays between the inputs and the outputs of the combinatorial part of the circuit provide sufficient delay across the feedback loops.

Page 222


Bistable devices:– Two stable states:

• Q=0 : the device is reset (reset state)

• Q=1: the device is set (set state)

– A bistable device remains in one of two states indefinitely until directed by an input signal to change state.

– Two types:

• Latch

• Flip-flop

Page 223


Latch: transparency property:– Change state when the input values change

– The new output state is delayed only by the propagation time delays of the gates between inputs and outputs of the latch.

– Used to implement the memory part of asynchronous circuits.

Flip-flop: no transparency property– Has a control (triggering) input, called clock.

– The state change only in response to a transition of a clock pulse at clock input.

– Used to implement memory part of synchronous circuits

Page 224

SR Latch

Two inputs: S (set), R (reset)

Two complementary outputs: Q, Q’

S Q

R Q’

Q

Q'

S

R

-1 1 1

-1 1 0

11 0 1

11 0 0

00 1 1

00 1 0

10 0 1

00 0 0

Q+S R Q

Indeterminate

Next state

Current state

Q = (R+Q’)’Q’= (S+Q)’

Page 225

SR Latch S Q

R Q’

Q

Q'

S

RIndeterminate1 1

11 0

00 1

Q0 0

Q+S R

Equivalent characteristic table

SR=’00’ => Output no changeA logic ‘1’ at inputs can change outputs’ states => active-HIGH latch

Page 226

SR Latch

S Q

R Q’

Q

Q'

S

R

active-HIGH SR Latch

S Q

R Q’

S

R

Q

Q'

active-LOW SR Latch

Page 227

SR Latch

Timing chart (NOR implementation)

S

R

Q

Qset reset resetset

Q

Q'

S

R

Page 228

SR Latch

Timing chart (NAND implementation)

Q

Q

S

R

set reset set reset

S

R

Q

Q'

Page 229

SR Latch

R

S

Q

Circuit showing feedback

Q+ = R’Q + R’S

SR=0 => Q+ = R’Q + R’S + RS = R’Q + Sfor active-HIGH SR Latch

- 01 1

0 11 0

1 00 1

0 -0 0

S RQ Q+

Excitation table

Page 230

D Latch

D Q

Q’

S Q

R Q’

D

11

00

Q*D

11 1

01 0

10 1

00 0

DQ Q*

Graphic symbol Implementation using SR Latch

Equivalent characteristic table

Excitation tableQ* = D

Page 231

Gated Latches

S Q E

R Q’

S

R

Q

Q'

E

E: Enable input control

The latch will not change state as long as E=0

E=1 SR=10 => SetE=1 SR=01 => Reset

⇒The operation of latch is synchronizedwith the E input => E: synchronous input

A latch with synchronous input is calledgated latch.

Page 232

Flip-flops

Latches implement memory part in asynchronous sequential circuits

Flip-flops do the same for synchronous circuits. FF has clock input and changes state synchronously with clock.

Four common types of flip-flops:– SR

– D

– JK

– T

Page 233

SR flip-flop

The triangle called dynamic indicator, indicates that the device responds only to an input clock transition from LOW (0) to HIGH (1) => Positive edge-triggered

Appending a small circle to the CLK input indicates that the flip-flop responds only to an input clock transition from HIGH (1) to LOW (0) => Negative edge-triggered

S Q CLK

R Q

S Q CLK

R Q

S Q CLK

R Q

Positive edge-triggered Negative edge-triggered Pulse-triggered(Master-Slave)

Page 234

SR flip-flop

The information is entered on the leading edge of the clock pulse, but the flip-flop does change state (the output is postponed) until the trailing edge of the clock pulse.

S Q CLK

R Q’

Pulse-triggered(Master-Slave)

Difference between Latch and Flip-flop?

• The flip-flop can not change state except on the triggering edge of clock pulse => synchronous• Present and next states in a latch are separated In time by gate delays, they are separated by clockperiods in a flip-flop.

Page 235

SR flip-flop

-1 1 1

-1 1 0

11 0 1

11 0 0

00 1 1

00 1 0

10 0 1

00 0 0

Q(t+1)S R Q

Indeterminate

Next stateCurrent state

Indeterminate1 1

11 0

00 1

Q(t)0 0

Q(t+1)S R

Characteristic table

Reduced characteristic table

- 01 1

0 11 0

1 00 1

0 -0 0

S RQ Q(t+1)

Excitation table

Q(t+1) = R’Q(t) + S(S=1 & R=1) is inhibited

Page 236

Implementation of SR-FF

CL

S 　Q

R 　Q

Q

Q

S

R

SR-latch

Q

Q

CL

S

R

Implementation of SR-FF by SR-Latch

Page 237

SR flip-flop

Timing chart

Q

Q

S

R

CL

S Q CLK

R Q

Page 238

D flip-flop

D flip-flop is useful for storing a single bit

D Q CLK

Q’

S Q CLK

R Q

D

CLK

Positive edge-triggered D flip-flop Implementation using SR flip-flop

Page 239

D flip-flop

11 1

11 0

00 1

00 0

Q(t+1)D Q


11

00

Q(t+1)D

Characteristic tableReduced characteristic table

11 1

01 0

10 1

00 0

DQ Q(t+1)

Excitation table

Q(t+1) = D

Page 240

JK flip-flop

JK = 00 => Q* = Q REMEMBER

JK = 01 => Q* = 0 RESET

JK = 10 => Q* = 1 SET

JK = 11 => Q* = not(Q) INVERT

J Q CLK

K Q’

S Q CLK

R Q

Positive edge-triggered JK flip-flop Implementation using SR flip-flop

Page 241

JK flip-flop

01 1 1

11 1 0

11 0 1

11 0 0

00 1 1

00 1 0

10 0 1

00 0 0

Q(t+1)J K Q


[Q(t)]’1 1

11 0

00 1

Q(t)0 0

Q(t+1)J K

Characteristic table

Reduced characteristic table

- 01 1

- 11 0

1 -0 1

0 -0 0

J KQ Q(t+1)

Excitation table

Q(t+1) = K’Q + JQ’

Page 242

Master-Slave flip-flop

A pulse-triggered flip-flop is a bistable device

– states depend on the values of synchronous inputs at the leading edge of the clock pulse

– those states does not change until the trailling edge of the clock pulse.

Page 243

Master-Slave flip-flop

A pulse-triggered flip-flop consists of two latches, where one acts as a master and the other acts as a slave => Master-slave flip-flop

S Q E

R Q’

S Q E

R Q’

Master SlaveS

C

R

Q

Q’

Master latch works when C=1Slave latch works when C=0

Page 244

Edge-Triggered flip-flop

A edge-triggered flip-flop is a bistable device whose state depends on the synchronous inputs either at the positive edge or at the negative edge of a clock pulse.

Page 245


Positive edge-triggered D flip-flop

Q

Q

CLK

D

Y1

Y2

Page 246


Positive edge-triggered JK flip-flop

Q

Q

CLK

J

K

Page 247

Flip-Flop conversions

Each FF can mutually convertedHow to implement y-FF by using x-FF(1) Prepare expanded state table of y-FF(2) Prepare excitation table of x-FF(3) Combine (1) and (2) (4) Calculate logic function for each input of x-ff

input of y-FF

a 　Q　　

b Q

Q

Qcom

binatorialcircuit

x-FFCL

CL

Page 248


Example: Implement T-FF using SR-FF

S R Q Q+0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 -1 1 1 -

Expanded state table shows the state transition by the input

T Q 0 0 0 1 1 0 1 1

Q+0110

T-FFSR-FF

Page 249



state　　　　　 inputQ　　 Q+　　 S 　　 R0 0 0 -0 1 1 01 0 0 11 1 - 0

SR-FF

S R Q Q+0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 -1 1 1 -

expanded state table excitation table

Excitation table shows the input value corresponding to the state transition

Page 250



T Q 0 0 0 1 1 0 1 1

Q+0110

T-FFstate　　　 inputQ　　 Q+　　 T0 0 0 0 1 1 1 0 1 1 1 0

excitation table

Page 251



T Q 0 0 0 1 1 0 1 1

Q+0110 T Q Q+ S R

0 0 0 　 0 -0 1 1 - 01 0 1 1 01 1 0 0 1

state　　　　　 inputQ　　 Q+　　 S 　　 R0 0 0 -0 1 1 01 0 0 11 1 - 0

expanded state table of T-FF

excitation table of SR-FF

Page 252



Calculate logic function for FF input

0

1

0 1TQ

- 0

0 1

0

1

0 1TQ

0 -

1 0

Karnaugh Map of R Karnaugh Map of S

R=TQ S=TQ

T

S Q

R Q

Q

Q

T Q Q+ S R0 0 0 　 0 -0 1 1 - 01 0 1 1 01 1 0 0 1

CL

CL

Page 253


Example: Implement D flip-flop using JK FF

D Q 0 0 0 1 1 0 1 1

Q+0011

D Q Q+ J K0 0 0 　 0 -0 1 0 - 11 0 1 1 -1 1 1 - 0

state 　　　 inputQ　　 Q+ 　　 J K 0 0 0 - 0 1 1 -1 0 - 1 1 1 - 0

excitation table of JK-FF

expanded state table of D-FF

Page 254


Example: Implement D flip-flop using JK FF

D Q Q+ J K0 0 0 　 0 -0 1 0 - 11 0 1 1 - 1 1 1 - 0

0

1

0 1DQ

- 1

1 -

0

1

0 1DQ

0 - - 0

Karnaugh Map of J Karnaugh Map of K

J=D K=D

D

J Q

K Q

Q

Q

CLCL

Page 255


4.1 Definitions






Page 256

Flip flop excitation equation

Flip Flop excitation equation express each synchronous input of each flip-flop as a function of the present state and the inputs of the circuit.

These Boolean functions are derived directly from the combinational part of the circuit.

Page 257

Analysis procedure of sequential circuits

S1. Find excitation equations, and output equations.

S2. Establish state table.

S3. Establish state diagram.

Page 258

Example1: A D flip-flop Moore model circuit

Excitation equations:– D1 = q1q2’ + xq1’

– D2 = xq1

Output equations: – z = q2’

1D 1Q

~1Q

~1CLR

1CLK

~1PR

1D 1Q

~1Q

~1CLR

1CLK

~1PR

x

Cl ock

z

q1 q2D1 D2

Since output is only a function of state z=q2’, and not directlyof input, this is Moore model

Page 259

Example1: A D flip-flop Moore model circuit

0010011

1111010

0100001

1100000

zx=1x=0

q1q2q1*q2*

001

101

010

110

0

0 0

0

1 1

1

1

State table

State diagram

q1* = d1 = q1q2’ + xq1’q2* = d2 = xq1

Page 260

Example2: A JK flip-flop Moore model circuit

Excitation equations: – JA = x KA = xB’

– JB = KB = x + A’

Output equations: – z = A + B

1J 1Q

~1Q1K

~1CLR

1CLK

~1PR

1J 1Q

~1Q1K

~1CLR

1CLK

~1PRx

Cl ock

A B

z

Since output is only a function of state z=A+B, and not directlyof input, this is Moore model

Page 261


1101111

1011010

1100001

0110100

zx=1x=0

ABA*B*

000

101

011 11

1

0

0

0

0

1 1

1

1

State table

State diagram

A* = A’JA + AKA= A’x+AxB’B* = B’JB + BKB = B’(x+A’) + B(x+A’)’

Page 262


Page 263

Example3: A D flip-flop Mealy model circuit

Excitation equations:– d1 = xq1 + xq2

– d2 = xq1’q2’

Output equations:– z = xq1

1D 1Q

~1Q

~1CLR

1CLK

~1PR

1D 1Q

~1Q

~1CLR

1CLK

~1PR

x

Cl ock

q1 q2

z

Since output is a function of both present input and state z=xq1, this is Mealy model

Page 264


10100011

10100010

00100001

00010000

x=1x=0x=1x=0q

zq*

q1* = d1 = xq1 + xq2q2* = d2 = xq1’q2’

00 11

01 10

0/0

0/0

1/0

0/00/0

1/0

1/1

1/1

Notice that:2. State 11 is never reached, this example really only has 3 states.2. Whenever there is a 0 input, we return tostate 00.

Page 265


Mealy timing trace:

00011000000z

000010010?q2

011100100?q1

011110110x

Page 266


Page 267


4.1 Definitions






Page 268

Design Procedure for Sequential Systems

S1. From a word description, determine what needs to be stored in memory, that is, what are the possible states.

S2. If necessary, code the inputs and outputs in binary.

S3. Derive a state table or state diagram to describe the behavior of the system.

S4. Use state reduction techniques to find a state table that produces the same input/output behavior, but has fewer states.

S5. Choose a state assignment, that is, code the states in binary.

S6. Choose a flip flop type and derive the flip flop input maps or tables.

S7. Produce the logic equation and draw a block diagram.

Page 269

Example1: Design sync sequential circuit using JK

Design a synchronous sequential circuit using JK flip-flop. The circuit has one input x, one output y. Output is 1 when receiving a string 0101 in input, otherwhile y=0.

Use Mealy model Systemx=0101011.. y=0001010..

1/0

A B C D0/0

1/0 0/0 0/0

0/0

1/0

1/1

A: wait for first 0B: had 0, wait for 1C: had 01, wait for 0D: had 010, wait for 1

Page 270


C,1B,0D

A,0D,0C

C,0B,0B

A,0B,0A

10x

S

Use two state variables q1q2

to encode states in binary

State table after assignment

State table

DB1

CA0

10q1

q2

10,101,011

00,011,010

10,001,001

00,001,000

10x

q1q2

Q1Q2 Q1Q2

Page 271


00,011,010

10,101,011

10,001,001

00,001,000

10x

q1q2

0-11

1-01

-110

-000

KJq*q

q1q2

x

0 1

J1K1 J2K2 J1K1J2K2

00 0 - 1- 0 - 0 -

01 0 - - 0 1 - - 1

11 - 1 - 0 - 0 - 1

10 - 0 1 - - 1 0 -

q1*q2*

Excitation table

Application table

Page 272


q1q2

x

0 1

J1K1 J2K2 J1K1 J2K2

00 0 - 1- 0 - 0 -

01 0 - - 0 1 - - 1

11 - 1 - 0 - 0 - 1

10 - 0 1 - - 1 0 -

Excitation equations:

xq1q2

0 1

00 0 0

01 0 1

11 - -

10 - - J1 = xq2

xqqxK 221 +=xJ 2 = K2 = x

Output equation: y = xq1q2

Minimization for J1

Page 273

Ex 1: Design sync sequential circuit using JK

J2 q2

CLK

K2 q2

J1 q1

CLK

K1 q1

1 &

=1

&

yx

CLOCK

Page 274


Design a synchronous sequential circuit using JK flip-flop. The circuit has one input x, one output y. Output is 1 when receiving a string 0111 in input, otherwhile y=0.

Page 275


Design a synchronous up/down counter using JK with one input x. If x=0 the circuit counts up from 0 to 3 and repeat, if x=1 the circuit counts down from 3 downto 0 and repeat.

Page 276









Page 277

S4. State reduction

State transition diagram may include redundancy. State reduction technique aims to simplify sequential circuit by reducing redundancy of the state transition diagram.

Equivalence:

– two states are equivalent if output sequences are the same when the same input sequence is given

Method 1: Procedure to get equivalent states

Method 2: Reduction of incompletely specified state table

Page 278

State reduction

Examples:

0/0

D

C

A

B

E

F

1/0

0/01/1

0/01/1

0/0

1/01/0

0/0 1/00/0 D

CB

E

AF

0/01/1

0/01/1

0/0

1/01/0

0/0 1/00/0

unify A and F

A and F have the same output and transition state for the same input

Page 279

State reduction

Examples:

D

CB

E

AF

0/01/1

0/01/1

0/0

1/01/0

0/0 1/00/0

unify D and E

CB

AF DE

0/01/0

1/00/0

0/01/1

0/01/1

D and E have the same output and transition state for the same input

Page 280

State reduction

Examples:

unify B and C

CB

AF DE

0/01/0

1/00/0

0/01/1

0/01/1

BC

AF DE 0/01/0

0/01/1

0/01/0

Page 281

State reduction

0 1 B C D E E D D FE FB C

0 1 0 0 0 1 0 1 0 00 00 0

ABCDEF

currentstate

next state output

0 1 B C D E E D D AFE AF

0 1 0 0 0 1 0 1 0 00 0

AFBCDE

0 1 B C DE DE DE DE DE AF

0 1 0 0 0 1 0 1 0 0

AFBCDE

0 1 BC BC DE DE DE AF

0 1 0 0 0 1 0 0

AFBCDE

currentstate

currentstate

currentstate

next state

next state next state

output

output output

Page 282

State reduction

Method 1: Procedure to get equivalent states

– (1) Find multiple states that have the same output with the same input, and treat them as a set of state S1 (s1,s2,…)

– (2) Rewrite state transition table by using the set of state.

– (3) If the next state of the member of the set are different,the set includes nonequivalent state. Then divide the nonequivalent set and iterate (2)

Page 283

Example of method 1 (1/4)

Reduce the state of the state transition diagram

a

f

e

d

c

b

1/0

0/0

0/1

1/1

1/0

0/11/1

0/0

0/1

1/1

1/0 0/1

0 1 a b d c a b f ed ce a

0 1 0 0 4 1 0 0 1 11 11 0

abcdef

currentstate

next state output

Page 284


(1) Find a set of statewith the same output

S1 (a,c)S2 (b,d,e)S3 (f)

(2) Rewrite next state by using set of state

a : S1,S2c : S1,S2

b : S2,S1d : S3,S2e : S2,S1

f : S2,S1

S1

S2

S3

(b,e) and d are not equivakenthence, divide S2 into S2 and S4

a : S1,S2c : S1,S2

b : S4,S1e : S4,S1

f : S2,S1

S1

S2

S3

S4 d : S3,S2

equivalent

equivalent


0 1 0 0 4 1 0 0 1 11 11 0

abcdef

currentstate

next state output

Page 285



0 1 0 0 4 1 0 0 1 11 11 0

abcdef

currentstate

next state output a : S1,S2c : S1,S2

b : S4,S1e : S4,S1

f : S2,S1

S1

S2

S3

S4 d : S3,S2

(2) Rewrite state transition table

0 1 S1 S2 S4 S1 S3 S2 S2 S1

0 1 0 0 4 1 1 1 1 0

S1S2S4S3

currentstate

next state output

Page 286


a

f

e

d

c

b

1/0

0/0

0/1

1/1

1/0

0/11/1

0/0

0/1

1/1

0/1 1

32

4

1/0

0/0

0/1

0/1

0/1

1/1

1/11/0

Generate state transition diagram 0 1 S1 S2 S4 S1 S3 S2 S2 S1

0 1 0 0 4 1 1 1 1 0

S1S2S4S3

currentstate

next state output

Page 287

State reduction

Method 2: Reduction of incompletely specified state table

– 1: Find non compatible pairs

– 2: Find compatible set that doesn’t involve non compatible pairs

– 3: Obtain maximum compatible set

– 4: Calculate minimum closed set

– 5: Generate reduced state transition table

Incompletely specified: don’t care appears in the next state and output

compatible pair: for every input, output are the same

Page 288


currentstate

next stateinput X1X000 01 10 11d e b -e - - aa - - e- b e da b f -d c - e

outputinput X1X0

00 01 10 110 - 0 -- 1 - 01 - 0 -- 0 0 -- - - 01 - 1 0

abcdef

a set of not compatible pairs(a,c) (a,f) (b,d) (c,f) (d,f)

Implication table

a b c d e

b

c

d

ef

×

×

×

× ×

1:fill in × at incompatible pair2: fill in conditions to be compatible

de

beadbebf

ae

aedeae

de

○ efadbc

Page 289


(a,b,e)

(a,b,c,d,e,f)

(a,b,d,e,f) (b,c,d,e,f)

(a,c)

(a,f)

(a,b,d,e) (b,d,e,f)

(b,d)

(b,c,e,f) (c,d,e,f)

(b,d)

(a,d,e)

(b,d)

(b,e,f) (d,e,f)

(c,f)

(b,e,f)(b,c,e)

(c,f)

(c,d,e) (d,e,f)

(d,f)

(d,e) (e,f)

Maximum compatible set is (a,b,e),(a,d,e),(b,e,f),(b,c,e),(c,d,e)

Decompose state set by non compatible pairs(a,c) (a,f) (b,d) (c,f) (d,f)

remove duplicated noderemove pair involved toother node

Page 290


Maximum compatible setC1:(a,b,e)C2:(a,d,e)C3:(b,e,f)C4:(b,c,e)C5:(c,d,e)

Logic function to represent each set involveda: C1+C2b: C1+C3+C4c: C4+C5d: C2+C5e: C1+C2+C4+C5f: C3

Minimum closed set is a subset of maximum compatible set that involves all the stateaxbxcxdxexf = 1(C1+C2)(C1+C3+C4)(C4+C5)(C2+C5)(C1+C2+C4+C5)C3=(C1+C2C3+C2C4)(C2C4+C5) (C1+C2+C4+C5)C3=(C1C5+C2C3C5+C2C4) (C1+C2+C4+C5)C3=(C1C5+C2C3C5+C2C4)C3=C1C3C5+C2C3C5+C2C3C4

hence (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) are candidates for minimum closed set

Page 291


C1:(a,b,e)C2:(a,d,e)C3:(b,e,f)C4:(b,c,e)C5:(c,d,e)

candidate for minimum closed set:(C1,C3,C5),(C2,C3,C5),(C2,C3,C4)

Implication table

a b c d e

b

c

d

ef

×

×

×

× ×

de

beadbebf

ae

aedeae

de

○ efadbc

check state transition of each candidate by using Implication table

C1→(d,e)(a,d),(b,e),(b,f),(a,e) →(a,d,e)(b,e,f) →C1,C3C2 →(b,e),(a,d),(b,e),(b,f),(e,f) →(b,e,f)(a,d) →C3,C2C3→(a,e),(d,e),(a,d),(b,c) →(a,d,e)(b,c) →C2,C4C4→(a,e) →(C1|C2)C5→(d,e),(e,f) →(C2|C5),C3

C2,C3,C4 is closed

Page 292


C2:(a,d,e),C3:(b,e,f),C4:(b,c,e) are used

currentstate

next stateinput X1X000 01 10 11d e b -e - - aa - - e- b e da b f -d c - e

outputinputX1X0

00 01 10 110 - 0 -- 1 - 01 - 0 -- 0 0 -- - - 01 - 1 0

abcdef

currentstate

next stateinput X1X000 01 10 11C2 C3 C3 C2C2 C4 C3 C2C2 C4 C3 C2

outputinput X1X0

00 01 10 110 0 0 01 1 1 01 1 0 0

C2C3C4

Reduced State Transition Table

Page 293









Page 294

State assignment

State assignment is to encode the state table into binary notation, the result is a transition table that combines next-state table and the output table.

Better state allocation results in an easy logic function for input of FF.

SP (Substitution Property): indicator for good state allocation.

a b c d

b da c

C

C1 C2

divide state into blocks so that the next state of the same block exists in the same block

state is allocated to distinguish blocksof SP

Page 295

State assignment

q1q2q3q4q5q6

q2q3q1q5q6q4

q4q6q5q2q1q3

input　 Xcurrentstate

next state

0 1

0 0 00 0 10 1 01 0 01 0 11 1 0

0 0 10 1 00 0 01 0 11 1 01 0 0

1 0 01 1 01 0 10 0 10 0 00 1 0

u u u u u u u u u

current state input　 Xnext state

0 11 2 3 1+ 2+ 3+1+2+ 3+

block 1 (q1,q2,q3)block 2 (q4,q5,q6)

This partition is SP

The first bit is used todistinguish the blocks.

Page 296

Chapter 5.

Hardware Design Languages

Page 297

Problems

Problem 1:

Design a synchronous up/down counter using JK with one input x. If x=0 the circuit counts up from 0 to 3 and repeat, if x=1 the circuit counts down from 3 downto 0 and repeat.

Problem 2:

Design a synchronous counter using JK with one input x. The circuit counts from 0 to 13 then repeat.

Problem 3:

Page 298

Problems for sequential circuit design

Textbook:

Chapter 6: 6.5

– 7a,b,c,d,

– 8a,b,c,d

– 9a,b,c,d

Chapter 7: 7.6

– 4,5,6,8,9,11,13,15

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