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3-Phase BLDC/PMSM Low VoltagePower Stage User Guide

Devices Supported:MC33937A

Document Number: 3PHLVPSUGRevision 0

07/2012

2 Freescale Semiconductor

Petr Konvicny

Freescale Semiconductor

Roznov Czech System Center

About This BookThis document describes the 3-Phase BLDC/PMSM Low Voltage Power Stage, targeted for rapid development of motor control applications.

To locate any published updates for this document, refer to the Freescale websaite at: http://www.freescale.com/.

Revision History

Documentation

The MC33937A documentation is available at the Freescale web site, http://www.freescale.com. as follows:

• Data sheet — MC33937A modules in detail• Product briefs — device overview• Application notes — address specific design issues

Table i. Revision History

DateRevision

levelDescription

Page number(s)

08/2012 0 Initial release 30

MC33937A Controller Board, Revision

Freescale Semiconductor 3

http://www.freescale.com

http://www.freescale.com/coldfire/

MC33937A Controller Board, Revision


Chapter 1 Introduction1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31.2 Board architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Chapter 2 Interface Description2.1 Power Supply J1 and J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.2 UNI3 Interface J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.3 MC33937A Interface J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92.4 Motor connector J6, J7, J8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92.5 Braking chopper connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Chapter 3 Design Consideration3.1 3-phase power bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.2 DC Bus voltage and current feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.3 Over-current, under-voltage, and other safety functions . . . . . . . . . . . . . . . . . . . . . . . . .133.4 Back EMF signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143.5 Phase current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.6 Power supplies and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.7 Brake choppper circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Chapter 4 Electrical Characteristics



Introduction

Chapter 1 IntroductionFreescale’s embedded motion control series 3-Phase BLDC/PMSM Low Voltage Power Stage is an 8 V–50 V, 10 Amps, surface-mounted power stage. In combination with one of the embedded motion control series controller boards, it provides a software development platform that allows algorithms to be written and tested without the need to design and build a power stage. It supports speed and position sensing based on Hall sensors, resolver sensors, encoder sensors, and back electromotive force (BackEMF) signals for sensorless control.

The 3-Phase BLDC/PMSM Low Voltage Power Stage has an over-current protection. It is independent of the control board when you choose the internal MC33937A DC bus operational amplifier with an over-current comparator. You must therefore be careful when you drive low impedance motors. The current measuring circuitry is setup for ±10 Amps full scale. At ambient temperature (25 °C), the board remains within thermal limits when operating with output currents of up to 10 Amps continuous RMS.

Input connections are made via the 40-pin and 10-pin ribbon cable connectors J3 and J4. Pin assignments for the input connector are illustrated in Section 2.2, “UNI3 Interface J3.” Power connections to the motor are made on the 3-way connectors J6 (Phase A), J7 (Phase B), and J8 (Phase C). The input voltage requirements are met by a power supply of 8 V–50 V. The voltage should be within these limits. The board sustains a voltage of at least 8 V with a maximum of 58 V. The input power is supplied by means of the 2.1 mm jack connector J2 or clamp connector J1.

The following is summary of the information required to use the 3-Phase BLDC/PMSM Low Voltage. For design information, see Section Chapter 3, “Design Consideration.”

1.1 FeaturesThe 3-phase low voltage power stage features are:

• MC33937A MOSFET pre-driver

• Motor control interface:

— UNI-3

— MC33937A pre-driver

• Braking chopper circuit

• Phase and DC-Bus voltage and current sensing circuits

• DC-Bus over current protection

• +12 Vdc, +5 Vdc DC-DC converters

1.2 Board architectureThe 3-phase low voltage power stage contains basic building blocks. See Figure 1-1.

3-Phase BLDC/PMSM Low Voltage Power Stage, Revision

Freescale Semiconductor 1-3

Introduction

Figure 1-1. 3-Phase BLDC/PMSM Low Voltage Power Stage controller board block diagram

The board is supplied by VBAT voltage in the range of 8 V–50 V.


1-4 Freescale Semiconductor

Introduction

Figure 1-2. 3-phase BLDC/PMSM low voltage power stage block location



Introduction



Interface Description

Chapter 2 Interface DescriptionInputs and outputs are located on eight connectors and headers available on the board:

• Two power supply connectors J1 and J2

• Three-pin motor connector (J6, J7, J8)

• Two-pin brake connector J5

• 40-pin UNI3 connector J3

• 10-pin MC33937 interface connector J4

Pin descriptions for each connector and header are identified in the following information. Table 2-1 shows the pin assignments and signal descriptions for the UNI3 interface connector J3.

The 3-Phase BLDC/PMSM Low Voltage Power Stage contains several connectors and headers that serve for connecting the power supply for motor phases connections, and other functions.

The input power supply, attached to inputs J1 and J2, must be in the range 8 V–50 V DC.

The output for the motor is executed by the connectors J6, J7, and J8. For more details see Section 2.4, “Motor connector J6, J7, J8.”

Each connector and header is labelled on the top side of the board.

2.1 Power Supply J1 and J2The 3-Phase BLDC/PMSM Low Voltage Power Stage board can be supplied by either using the 2.1 mm DC power plug J2 or connector (J1).

The board provides 12 V, 5 V, and 3.3 V for board logic and analogue circuits, and for controllers boards connected through UNI-3 interface.

The board is designed to operate in the voltage range from 8 V–50 V. The board is protected against a reverse battery.

2.2 UNI3 Interface J3The Unified Interface Version 3 (UNI-3) defines the interface between the 3-Phase BLDC/PMSM Low Voltage Power Stage and the dedicated controller board.

The list of UNI-3 signals is as follows:

• Control signals:

— PWM phase A, B, C top and bottom switches control

— Braking chopper control signal

— Power Factor Correction (PFC)

• Monitor signals

— DC-bus voltage

— DC-bus current




— Phase A, B, C current

— Zero-cross signals

— Back-EMF phase A, B, C

— Temperature monitoring

• Power Supply 12 V

• Serial line — A bidirectional communication line between the Controller Board and Power Stage

Table 2-1 defines the UNI-3 pin-out.

Table 2-1. UNI-3 signal description

Interface Pin Signal Name MCU Signal Description Direction

1 PWM_AT – Phase A top switch control (H -> Turn OFF) Digital input

3 PWM_AB – Phase A bottom switch control (H -> Turn ON) Digital input

5 PWM_BT – Phase B top switch control (H -> Turn OFF) Digital input

7 PWM_BB – Phase B bottom switch control (H -> Turn ON) Digital input

9 PWM_CT – Phase C top switch control (H -> Turn OFF) Digital input

11 PWM_CB – Phase C bottom switch control (H -> Turn ON) Digital input

2, 4, 6, 8, 10 Shield– PWM signals shield

(grounded on the power stage side only)–

12,13 GND_D – Digital power supply ground –

14, 15 +5 V DC – +5 V digital power supply –

17, 18 AGND – Analog power supply ground –

19 +12/+15 V DC – Analog power supply –

16,20, 27, 28,37 NC – Not connected –

21 VDCBUS – DC-bus voltage sensing, 0 V – 3.3 V Analog output

22 IDCBUS – DC-bus current sensing, 0V – 3.3V Analog output

232425

IAIBIC

– Phase A current sensing, 0 – 3.3 VPhase B current sensing, 0 – 3.3 VPhase C current sensing, 0 – 3.3 V

Analog output

26 TEMP – Analog temperature 0 V – 3.3 V Analog output

29 BRAKE_CONT – DC-bus brake control Digital input

30 SERIAL – Serial interface Dig. bidirectional

31 PFC – Power factor correction PWM Digital input

32 PFCEN – Power factor correction enable Digital input

33 PFCZC – Power factor correction Zero-cross Digital output

34 ZCA – Phase A Back-EMF zero crossing Digital output

35 ZCB – Phase B Back-EMF zero crossing Digital output

36 ZCC – Phase C Back-EMF zero crossing Digital output




2.3 MC33937A Interface J4The phase top and bottom switches are controlled by the MC33937A pre-driver. The device is configured by the SPI, see Table 2-2.

2.4 Motor connector J6, J7, J8Power outputs to the motor are located on connectors J6, J7, and J8. Phase outputs are labelled A, B, and C. A permanent magnet synchronous or brushless DC motor phase windings can be connected to the connectors J6, J7, and J8. Table 2-3 contains pin assignments.

38 Back-EMF_A – Phase A Back-EMF voltage sensing Analog output

39 Back-EMF_B PAD2 Phase B Back-EMF voltage sensing Analog output

40 Back-EMF_C PAD4 Phase C Back-EMF voltage sensing Analog output

Table 2-2. MC33937A signal description


1 NC – Not connected –

2 NC – Not connected –

3 MC33937_EN – Device enable Digital input

4 MC33937_OC – Over current. Totem pole digital output of overcurrent comparator

Digital output

5 MC33937_/RST – Reset input Digital input

6 MC33937_INT – Interrupt pin output Digital output

7 MC33937_SOUT – Output data for SPI port. Tri-state until CS becomes low

Digital output

8 MC33937_SCK – Clock for the SPI port Digital input

9 MC33937_CS – Chip select input. It frames the SPI command and enables the SPI port

Digital input

10 MC33937_SIN – Input data for the SPI port. Clocked on the falling edge of SCLK, MSB first

Digital input

Table 2-3. Motor Connector — signal description

Pin Signal name Description

J6 Phase A Supplies power to motor phase A

J7 Phase B Supplies power to motor phase B

J8 Phase C Supplies power to motor phase C

Table 2-1. UNI-3 signal description (continued)





2.5 Braking chopper connector J5The braking resistor can be joined to connector J5. This is located on the left top corner of the board.

Table 2-4. Brake resistor connector — signal description

Pin Signal name Description

1 – Brake_res Brake resistor negative terminal

2 + Brake_res Brake resistor positive terminal



Design Consideration

Chapter 3 Design ConsiderationThe 3-phase BLDC/PMSM low voltage power stage demonstrates the ability of Freescale microcontrollers and DSCs to control various electrical motors and for easy SW development. In addition to the hardware needed to run a motor, a variety of feedback signals that facilitate control-algorithm development are provided. A set of schematics for the drive is explained in the following section.

3.1 3-phase power bridgeThe power stage is configured as a 3-phase power bridge with MOSFET output transistors. It is simplified considerably by an integrated gate driver that has several safety features. Figure 3-1 shows a schematic of the 3-phase power bridge. The pre-driver inputs are 3.3 V compatible. A Freescale MC33937 pre-driver provides a supply voltage for the low and high side MOSFET gates. The MC33937 also provides the MOSFETs and application protection. It integrates an under voltage hold-off, desaturation, phase comparators, and over-current protection circuits. The dead time insertion can be configured using SPI. The default dead time value is typically 15 us. The low and high side drivers are capable of providing a typical current of 1 Amp. This gate drive current may be limited by an external resistor to achieve a good trade-off between the efficiency and EMC compliance of the application.

Figure 3-1. 3-phase power bridge




3.2 DC Bus voltage and current feedbackFigure 3-2 shows the circuity that provides feedback signals proportional to DC bus voltage and current. Bus voltage is scaled down by a voltage divider consisting of R40, R42. The populated resistor values are chosen in such way that a 50.05 V, 36.025 V, or 18.298 V DC bus voltage corresponds to VREF at output V_DCBUS. This output signal is connected to the UNI3 connector pin 21.

Figure 4-2 shows the circuitry supporting DC bus current sensing. The DC bus current is sampled by shunt resistor R33. The voltage drop for this resistor can be amplified by either the MC33937 internal amplifier or an AD8656 operational amplifier (if populated). Both amplifiers are used as a differential amplifier for DC bus current sensing. With R46=R52, and R48=R50, the gain is given by:

The output voltage is shifted up by +1.65V VREF to accommodate positive and negative current swings. A ±150mV voltage drop across the sense resistor corresponds to a measured current range of ±10Amps.

If you use the MC33937 for current measurement, the I_DCBUS signal is internally connected to the over current comparator, and provides an over current triggering function. A discussion about over-current limiting follows in section 3.3.

The DC bus current may be measured by an AD8656. To use this option, the zero resistors R35, R36 and R37 cannot be populated. MC33937 operational amplifier inputs must be grounded to avoid incorrect OC output behavior.

The output from opam I_DCBUS is joined to the UNI3 connector pin 22. The shunt resistor is represented by a 0.015 resistance (Cyntec SMD), the same type as the phase current measurement resistors.

AR46R48----------=




Figure 3-2. DC Bus current and voltage sensing

3.3 Over-current, under-voltage, and other safety functions

The MC33937A provides over-current and under-voltage functions. The amplified DC Bus current signal is filtered to remove spikes, and then it is internally fed into the MC33937 over-current comparator input. The OC comparator threshold level is adjusted by external trimmer R38 and filtered by C43. This signal is connected to the MC33937 pin 28 OC_TH. Therefore, when DC bus current exceeds the adjusted threshold level, all six bridge transistors are switched off. After a fault state has been detected, all six gate drivers are off, until the fault state is cleared by the SPI command or RESET pin.

The under voltage function is implemented internally. The IC guarantees that the output FETs are turned off in the absence of VDD or VPWR by means of the Hold-off circuit. When VDD is less than about 3.0 V or VPWR is lower than the typically 8.0 V, a small current source pulls all output gate drive pins low and if set an interrupt is generated.

The MC33937A safety functions keep the driver operating properly and within safety limits. It has a thermal warning feature. If the IC temperature rises above 170 °C on one of three individual thermal warning circuits, then an interrupt is generated if set. The IC has other safety functions, such as desaturation detection, phase error, framing error, write error after a lock, and exiting RESET. All these features can be configured through the SPI interface to trigger interrupts.




A detailed description is available in the driver datasheet.

Figure 3-3. MC33937A circuit

3.4 Back EMF signalsBack EMF signals are included to support sensorless algorithms for BLDC motors, and dead time distortion correction for a sinusoidal motor. Figure 3-4 shows circuitry for phase A; the raw phase voltage is scaled down by a voltage divider consisting of R55 (R67 or R70) and R60. Output from this divider produces a a back EMF sense voltage BEMF_A. The resistor values are chosen so that a 50.05 V, 36.025 V or 18.298 V of phase voltage corresponds to a 3.3 V ADC input range. The BEMF_A, BEMF_B, BEMF_C signals are directly connected to the UNI3 interface pins 38, 39, 40.

Figure 3-4. Back EMF Sensing — Phase A, B, C




3.5 Phase current sensing

Phase currents are sampled by sensing resistors R30, R31, R32 in Figure 3-5, and amplified in the U5, U6 (AD8656) operational amplifiers. All amplifiers are used as a differential for phase current sensing. With R41=R43, R39=R44, the gain is given by:

The gain of these operational amplifiers are 11 with a +1.65 V offset. The output voltage is shifted up by +1.65 V VREF to accommodate positive and negative current swings. A ±150 mV voltage drop across the sense resistor corresponds to a measured current range of ±10Amps.

The outputs from opams I_A, I_B, I_C are connected to the UNI3 connector pins 23, 24, 25 through RC filters R13, C24. The shunt resistor is represented by a 0.015 resistance (Cyntec SMD), the same shunt resistor is used for DC bus current measurement.

Figure 3-5. Phase current sensing circuit

3.6 Power supplies and voltage reference

The 3-phase BLDC/PMSM low voltage power stage contains devices that require various voltage levels of +12 V, +5 V, and +3.3 V.

3.6.1 Input power supply

The DC bus can be supplied from two input connectors, J1 and J2. The DC bus has reverse polarity protection. The MC33937 driver is supplied from a SEPIC DC/DC converter that delivers a constant output voltage of +12 V across the entire input voltage range (+8 V to +50 V). The +5 V and +3.3 V power supplies are taken from +12 V source.

3.6.2 +12 V power supply

The constant +12 V supply voltage for the wide input voltage range (6 V to 50 V) is provided by the SEPIC converter. This topology delivers a constant output voltage when the input voltage is below or above the

AR39R41----------=




nominal output voltage. It is suitable for this input voltage range. The LM5022 is a high voltage low side N-channel MOSFET controller. The output voltage regulation is based on current-mode control. It includes a start-up regulator that operates over a wide input range of 6 V to 60V, an error amplifier, precision reference, line under-voltage lockout, cycle-by-cycle current limit, slope compensation, soft-start, external synchronization capability, and thermal shutdown. The switching frequency has been setup to 500 kHz.

3.6.3 +5 V power supply

The +5 V voltage level is generated by the step down DC/DC converter LM2694. This circuit delivers up to 600 mA peak output current. The switching frequency is adjusted to 500 kHz. More information is available in the converter datasheet.

3.6.4 +3.3 V power supply

An important voltage level for this board is +3.3 V. This is obtained from the MC33269D linear voltage regulator, which is able to deliver up to 800 mA. The +3.3 V level is used to supply the on-board analogue devices.

3.6.5 +1.65 V voltage reference

The +1.65 V reference is generated from the +3.3 V level by a resistors divider and an impedance isolator. This reference shifts all current sensing output signals by 1.65 V.

3.7 Brake choppper circuitThe brake chopper circuit is included to control the operation of losing the energy from the motor through regenerative braking to an external brake resistor.

There is only a power switch with a pre-driver and a freewheeling diode populated on the board. An external brake resistor must connected through the two pin connector J5.



Electrical Characteristics

Chapter 4 Electrical CharacteristicsThe electrical characteristics in Table 4-1 apply to an operation at 25 °C.

1—measured at 12 V power supply2—The values are measured at 25 °C. Values may differ for other temperatures.

Table 4-1. Electrical Characteristics

Characteristic Symbol Minimum Type Maximum Units

Power supply Voltage VDC 8 12, 24, 42 58 V

Quiescent Current(1) ICC – TBD – mA

Min Logic 1 Input Voltage VIH – – – mA

Max Logic 0 Input Voltage VIL – – – mA

Input Logic Resistance RIN – 4.7 – k

Analogue Output Range VOUT 0 - 3.3 V

Bus Current Sense Voltage VISNS – 165 – mV/A

Bus Current Sense Offset VISNSOFF – 1.65 – V

Bus Voltage Sense Voltage: ............. 12 V range24 V range48 V range

VBUS 5.356410.720314.8861

5.444510.916715.1667

5.534211.11715.4529

V/V

Phase A, B, C Current Sense Voltage VIASNS – 165 – mV/A

Phase A, B, C Current Sense Offset VIASNSOFF – 1.65 – V

Power MOSFET On Resistance RDS(ON) – 22.5 28.5 m

Continuous Output Current, TC =25 °C ID – 35 – A

Pulsed Output Current IDM – 140 – A

Total Power Dissipation (per MOSFET)(2) PD – TBD – W

Required Deadtime tOFF – 77 – ns




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3393

7_/R

ST

3393

7_IN

T

I_A

BR

AK

E_C

ON

T

I_B

I_C

V_D

CB

US

3393

7_E

N

3393

7_S

IN33

937_

SO

UT

3393

7_S

CK

3393

7_C

S

AG

ND

GN

D

DC

BU

S_P

OS

DC

BU

S_N

EG

3393

7_O

C




Figure 4-2. Schematic -— Input circuit and power supply

OU

TPU

T 12

Vdc

, 1 A

mps

R6 / R7 = 8.6 for 12V output

Rt for 500kHz

R18

/ R

17 =

3.9

for 6

.125

V U

VLO

thre

shol

d

curr

ent s

ense

circ

uit p

lace

as

clos

e as

pos

sibl

e to

LM

5022

+12V

dc

+3.3

VA

dc

AG

ND

GN

D

DC

BU

S_P

OS

DC

BU

S_N

EG

DC

BU

S_P

OS

DC

BU

S_P

OS

+3.3

VA

AG

ND

+12V

dc

+12V

dc

DC

BU

S_P

OS

DC

BU

S_N

EG

+12V

dc

AG

ND

+5V

Adc

+5V

dc

GN

D

Dra

win

g Ti

tle:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A3

Thur

sday

, Feb

ruar

y 02

, 201

2

Inpu

t circ

uit a

nd p

ower

sup

ply

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

25

x__

____

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A3

Thur

sday

, Feb

ruar

y 02

, 201

2

Inpu

t circ

uit a

nd p

ower

sup

ply

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

25

x__

____

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A3

Thur

sday

, Feb

ruar

y 02

, 201

2

Inpu

t circ

uit a

nd p

ower

sup

ply

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

25

x__

____

__

C16

0.1U

F

L1L2

L1

10U

H

1 342

U1

LM50

22

VC

C4

GN

D6

RT

9V

IN1

OU

T5

CS

8FB

2

CO

MP

3

UV

LO7

SS

10

R2

10.2

K

D1

MB

RD

620C

T

1 34

C9

220P

F

+C

1947

UF

R4

4.7

C13

0.02

2UF

+C

1847

UF

IC1

LM26

94

SW

1

BS

T2

ISE

N3

SG

ND

4

RTN

5FB

6S

S7

RO

N/S

D8

VC

C9

VIN

10

EP11

R1

3.90

K

C23

0.02

2UF

+C

433

UF

C5

0.1U

F

C20

10U

F

L2 50O

HM

12

R3

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BA

R1

Sho

rting

Bar

1206

C3

1UF

J1 CO

N_2

_TB

A1

B2

Q1

60V

1

324

R12

10.2

K

C14

22uF

R8

0.1

R6

1.0K

J2

CO

N_1

_PW

R

1 23

R9

1.2K

VIN

VO

UT

GN

D/A

DJ

U2

MC

3326

9DT-

3.3G

3

1

2

R11

75K

C11

1000

PF

C8

10U

F

+C

210

0UF

D3

MB

RA

160T

3G

21

C1

0.1U

F

R15

2.2

C10

0.22

UF

R5

33.2

K

D2

MB

RA

160T

3G

21

C7

10U

F

C12

1UF

C17

0.1U

F

R10

10.2

K

C21 0.1U

F

L3 150u

H1

2

C6

10U

F

R7

1.0K

C22

0.1U

F




Figure 4-3. Schematic — UNI-3 Interface

54

32

1

D C B AA

PW

M_A

TP

WM

_AB

PW

M_B

TP

WM

_BB

PW

M_C

TP

WM

_CB

V_D

CB

US

I_D

CB

US

I_B

I_A

I_C

BR

AK

E_C

ON

T

ZCB

ZCA

ZCC

BE

MF_

AB

EM

F_C

BE

MF_

B

3393

7_IN

T

3393

7_S

IN

3393

7_E

N33

937_

/RS

T33

937_

SO

UT

3393

7_C

S33

937_

SC

K

3393

7_O

C

GN

D

GN

DG

ND

AG

ND

AG

ND

AG

ND

GN

D

+12V

dc

+5V

Adc

+5V

dc+5

Vdc

AG

ND

Dra

win

g Ti

tle:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A4

Thur

sday

, Feb

ruar

y 02

, 201

2

UNI-3

Inte

rface

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

35

x__

____

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A4

Thur

sday

, Feb

ruar

y 02

, 201

2

UNI-3

Inte

rface

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

35

x__

____

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

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rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

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ritte

n pe

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sion

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rees

cale

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icon

duct

or.

ICA

P C

lass

ifica

tion:

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:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A4

Thur

sday

, Feb

ruar

y 02

, 201

2

UNI-3

Inte

rface

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

35

x__

____

__

J3 CO

N_2

X20

12

34 6

5 78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

J4 HD

R_2

X5

12

34 6

5 78

910




Figure 4-4. Schematic — 3ph power bridge with driver circuit

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Bra

ke S

witc

h

Pop

ulat

e R

35, R

36, R

37 o

r R77

, R78

.

Out

put t

erm

inal

ZC_A

ZC_B

ZC_C

3393

7_IN

T

3393

7_/R

ST

3393

7_E

N

PW

M_A

TP

WM

_BT

PW

M_C

T

PW

M_A

BP

WM

_BB

PW

M_C

B

3393

7_/C

S

3393

7_S

CLK

3393

7_S

O

3393

7_S

I

+12V

dc

+3.3

VA

dc

+12V

dc

BR

AK

E_C

ON

T

GN

D

DC

B_N

EG

DC

B_P

OS

3393

7_O

C_O

UT

GN

D

GN

D

DC

B_P

OS

DC

B_P

OS

GN

D

GN

D

GN

DG

ND

GN

D

VLS

GN

D

DC

B_P

OS

DC

B_N

EG

I_se

nse_

AP

I_se

nse_

AN

I_se

nse_

BP

I_se

nse_

BN

I_se

nse_

CP

I_se

nse_

CN

I_D

CB

US

_P

I_D

CB

US

_N

PA

_HS

S

PA

_HS

S

PA

_HS

G

PA

_HS

G

PA

_LS

G

PA

_LS

G

PA

_LS

S

PA

_LS

S

PB

_HS

G

PB

_HS

S

PB

_LS

G

PB

_LS

S

PB

_HS

G

PB

_LS

GP

B_H

SS

PB

_LS

SP

C_L

SS

PC

_HS

G

PC

_LS

GP

C_H

SS

PC

_HS

S

PC

_LS

G

PC

_LS

S

PC

_HS

G

3393

7_A

MP

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937_

AM

P_P

3393

7_A

MP

_OU

T

PA

_HS

S

PB

_HS

S

PC

_HS

S

BR

AK

E_G

ATE

BR

AK

E_G

ATE

Dra

win

g Ti

tle:

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eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

le o

r in

part

with

out t

he e

xpre

ss w

ritte

n pe

rmis

sion

of F

rees

cale

Sem

icon

duct

or.

ICA

P C

lass

ifica

tion:

FCP

:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A3

Thur

sday

, Feb

ruar

y 02

, 201

2

3ph

pow

er b

ridge

with

driv

er c

ircui

t

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

45

x__

____

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Pag

e Ti

tle:

Des

igne

r:

Dra

wn

by:

App

rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

e us

ed fo

ren

gine

erin

g de

sign

, pro

cure

men

t or m

anuf

actu

re in

who

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r in

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cale

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icon

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ICA

P C

lass

ifica

tion:

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:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A3

Thur

sday

, Feb

ruar

y 02

, 201

2

3ph

pow

er b

ridge

with

driv

er c

ircui

t

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

45

x__

____

__D

raw

ing

Title

:

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

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e Ti

tle:

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igne

r:

Dra

wn

by:

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rove

d:

Czec

h Sy

stem

Cen

tre1.

Maj

e 10

0975

661

Roz

nov

pod

Rad

host

em, C

zech

Rep

ublic

This

doc

umen

t con

tain

s in

form

atio

n pr

oprie

tary

to F

rees

cale

Sem

icon

duct

or a

nd s

hall

not b

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icon

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ICA

P C

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ifica

tion:

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:FI

UO

:P

UB

I:

SC

H-2

6777

PD

F: S

PF-

2677

7C

10A

Low

Vol

t. 3-

ph P

S w

ith M

C33

937

A3

Thur

sday

, Feb

ruar

y 02

, 201

2

3ph

pow

er b

ridge

with

driv

er c

ircui

t

Pet

r Kon

vicn

y

<App

rove

r>

Pet

r Kon

vicn

y

45

x__

____

__

R30

0.01

5

Q4

IRFR

540Z

1

34

R23

47

R78

0

R19

47

C40

0.15

UF

R31

0.01

5

C35

2.2U

F

R36

0 DN

P

C42

1000

pF

R21 47

TP10

Out

BIn

B

GN

D

InA

NC

NC

Out

A

VC

CU

4M

C33

152

2

3

5

6

781 4

C33

2.2U

F

D9

MM

SD

914T

121

+C

2768

.0U

F

D6

MM

SD

914T

121

R28 47

C34

0.1U

F

R35

0 DN

P

U3

PC

Z339

37A

EK

PH

AS

EA

1

PGND2

EN

13

EN

24

RS

T5

PUMP7

VPUMP8

VSUP9

PH

AS

EB

10P

HA

SE

C11

PA

_HS

12

PA

_LS

13

VDD14

PB

_LS

16

INT

17

CS

18

SI

19

SC

LK20

SO

21

PC

_LS

22

AM

P_O

UT

24

AM

P_N

25

AM

P_P

26

OC

_OU

T27

OC

_TH

28

VSS29

GND030

GND131

VLS_CAP32 PC_LS_S

34

PC

_LS

_G35

PC

_HS

_S36

PC

_HS

_G37

PC

_BO

OT

38

PB_LS_S39

PB

_LS

_G40

PB

_HS

_S41

PB

_HS

_G42

PB

_BO

OT

43

PA_LS_S44

PA

_LS

_G45

PA

_HS

_S46

PA

_HS

_G47

PA

_BO

OT

48

VLS51

NC

16

VPWR54

PB

_HS

15

PC

_HS

23

NC

233

NC

349

NC

450

NC

552

NC

653

EP55

R26 47

Q7

IRFR

540Z

1

34

R18

47

Q8

IRFR

540Z

1

34

C31

2.2U

F

Q2

IRFR

540Z

1

34

Q3

IRFR

540Z

1

34

R32

0.01

5

R37

0 DN

P

SHORT

J8

CO

N 1

TB

12

R20 47

D10

MB

R12

0LS

FT1G

AC

D5

MM

SD

914T

121

R22 47

+C

2868

.0U

F

D4

MM

SD

914T

121

SHORT

J7

CO

N 1

TB

12

C36

0.1U

F

J5 CO

N_2

_TB

A1

B2

R24 47

+

C39

22U

F

R16

47

R17

47

C37

0.1U

F

R29

47

SHORT

J6

CO

N 1

TB

12

R27 47

C41

0.15

UF

R38

10K

1 3

2

D8

MM

SD

914T

121

C38

0.15

UF

R25 47

R33

0.01

5

D13

MU

RA

110T

3

21

D7

MM

SD

914T

121

R77

0

C32

0.1U

F

C43

0.1U

F

Q5

IRFR

540Z

1

34

+C

3047

UF

R34

3.3K

Q6

IRFR

540Z

1

34




Figure 4-5. Schematic — Analogue sensing circuits

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DC

BU

S Vo

ltage

Sen

sing

3.3V

@ 5

0.05

V

(51k

/3.6

k)3.

3V @

36.

025V

(

35.7

k/3.

6k)

3.3V

@ 1

8.29

8V

(1

6k/3

.6k)

Dec

oupl

ing

capa

cito

r C48

Pla

ce a

s cl

ose

as p

ossi

ble

to V

+ pi

n

Dec

oupl

ing

capa

cito

rs C

44, C

45P

lace

as

clos

e as

pos

sibl

e to

V+

pin

3 Ph

ase

Cur

rent

Sen

sing

Ref

eren

ce d

ivid

er:

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log

supp

ly v

olta

ge is

div

ided

by

2;O

utpu

t vol

tage

is +

1.65

Vdc

Dec

oupl

ing

capa

cito

r C26

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ce a

s cl

ose

as p

ossi

ble

to V

+ pi

n

DC

BU

S C

urre

nt S

ensi

ng

Bac

k EM

F vo

ltage

sen

sing

3.3V

@ 5

0.05

V

(51k

/3.6

k)3.

3V @

36.

025V

(

35.7

k/3.

6k)

3.3V

@ 1

8.29

8V

(1

6k/3

.6k)

3.3V

@ 5

0.05

V

(51k

/3.6

k)3.

3V @

36.

025V

(

35.7

k/3.

6k)

3.3V

@ 1

8.29

8V

(1

6k/3

.6k)

3.3V

@ 5

0.05

V

(51k

/3.6

k)3.

3V @

36.

025V

(

35.7

k/3.

6k)

3.3V

@ 1

8.29

8V

(1

6k/3

.6k)

Do

not p

opul

ate:

R73

, C57

, R74

, C58

, R75

, C59

, R76

, C60

V_D

CB

US

I_A

I_B

I_C

I_D

CB

US

+3.3

VA

dc

AG

ND

BE

MF_

AB

EM

F_B

BE

MF_

C

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

+3.3

VA

+3.3

VA

+3.3

VA

+3.3

VA

+3.3

VA

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

DC

B_P

OS

I_se

nse_

AP

I_se

nse_

AN

I_se

nse_

BP

I_se

nse_

BN

I_se

nse_

CP

I_se

nse_

CN

I_D

CB

US

_P

I_D

CB

US

_N

PA

_HS

SP

B_H

SS

PC

_HS

S

3393

7_A

MP

_N

3393

7_A

MP

_P

3393

7_A

MP

_OU

T

+1.6

5Vre

f

+1.6

5Vre

f

+1.6

5Vre

f

+1.6

5Vre

f

+1.6

5Vre

f

Dra

win

g Ti

tle:

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rR

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of

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3.0K

TP1

TPA

D_0

50

R71

16.0

KD

NP

R51 33

k

R64

10.0

K

R53 33

k

R45 33

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R57

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R75

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P

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P

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C49

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R56

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KD

NP

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1.2k

DN

P

C48

0.1U

F

R66

16.0

KD

NP

R60

3.6K

C47

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F R44 33

k

R40

51.1

KD

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TP7

TPA

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50

C54

47P

F

R42

3.6K

R67

35.7

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R49

3.0K

R74

1.2k

DN

P

- +

V+

V-

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AD

8656

31

2

8 4

R76

1.2k

DN

P

R55

51.1

KD

NP

R54

3.0K

R48

3.0K

R68

35.7

K

C51

47P

F

C56

0.22

UF

C46

47P

F

TP6

TPA

D_0

50

C58

12P

FD

NP

C55

47P

F

+

C44

22U

F

C60 12

PF

DN

P

R50

3.0K

R52 33

k

- +

V+

V-

U5A

AD

8656

31

2

8 4

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35.7

K

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D_0

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PF

DN

P

- +

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57

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7016

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DN

P

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F

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K

R65

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K

TP3

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50

R46 33

k

C45

0.1U

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8656

57

6

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3.6K

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D_0

50




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