1 Pulsar firmware status June 11th, 2004 Slink format Transmitter firmware Transmitter firmware status Receiver firmware overview Receiver firmware status.

1

Pulsar firmware statusJune 11th, 2004

Slink format

Transmitter firmware

Transmitter firmware status

Receiver firmware overview

Receiver firmware status

New VME interface

Sakari Pitkänen, Tomi Mansikkala

2

Slink format

Formatversion

Datasource

RegionID

ReservedBunchcount

Buffer#

8 4 2 8 28

Data

Latency Data size

16 16

Data size Error flags

1616

• Second header word added

• Data size now also before data

• Space for latency information

3

• Sends data from RAM after receiving L1A from P2 backplane connection

• Has 1k or 4k word internal RAM where user can load test patterns thru VME (if SRAM is used, lots of more words can be loaded)

• Test pattern RAM not divided to four buffers anymore

RAM

Test pattern

Output FIFO

L1A with buffer #

data

data

latency

Transmitters are able to• Have delay before sending data out

max. delay time varies between ~8.5us to ~0.5s (depends on firmware)

• Have gaps between data words

• Have empty events

• Send same or different events on each L1A

Transmitter firmware

Tomi Mansikkala

4

New transmitter firmwares

- RECES TX (testing ongoing)

- ISOLIST TX (testing ongoing)

- MUON TX (testing ongoing)

- CLIST TX (not tested yet)

- XTRP TX (teststand tested, OK)

- SVT TX (teststand tested, OK)

Left to do

- SLINK TX

- L1T TX

Control FPGA

DataIO FPGA

DataIO FPGA

Transmitter firmware status

Tomi Mansikkala

5

PC

SLINK

Pulsar pre-processors

L1 muon

L1 XTRPL1 trigger

TS

L2 CAL(CLIST/Iso)

PreFred

ShowMax

(RECES)

SVT

Muon

Cluster

Reces

Recesmerger

SVT

L2toTS

Receiver firmware overview

Slinkmerger

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• Receives data from four Slink inputs• Saves data to input DAQ buffers• Merges data and creates one Slink package• Saves Slink formatted data to output DAQ buffers• Sends data out from P3 - AUX card - Slink

Slink merger

Slink inputsAUX cardSlink output

Four Slinkmezz cards

Status- A lot of teststand testing done- Beam tests ongoing

Merger header 2

Merger trailer

Input 1 header 1

Input 1 trailer

Input 2 header 1

Input 2 trailer

Input 3 header 1

Input 3 trailer

Input 4 header 1

Input 4 trailer

Slink input 1

data

Slink input 2

data

Slink input 3

data

Slink input 4

data

Input 1 header 2

End of fragm

ent

Input 2 header 2

Slink merger output

End of fragm

ent

Input 3 header 2

End of fragm

ent

Input 4 header 2

End of fragm

ent

0xE0F00000

Merger header 1

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Reces

• Receives data from 16 Taxi fibers• Saves data to input DAQ buffers• Zero suppresses Reces data (Phase I: no zero suppresion)• Merges data and creates one Slink package• Saves Slink formatted data to output DAQ buffer• Sends data out from P3 - AUX card - Slink

Taxi inputsAUX cardSlink output

Four Taximezz cards

Status- Teststand testing ongoing- Ready for beam tests

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Reces m

erger head

er 1

Reces 1 header 1

Reces 1 trailer

Reces 2 header 1

Reces 2 trailer

Reces 3 header 1

Reces 3 trailer

Reces P

ulsar 1data

Reces P

ulsar 2data

Reces P

ulsar 3data

Reces 1 header 2

End of fragm

ent

Reces 2 header 2

Reces merger output

End of fragm

ent

Reces 3 header 2

End of fragm

ent

Reces mergerM

erger header 2

Merger trailer

Input 1 header 1

Input 1 trailer

Input 2 header 1

Input 2 trailer

Input 3 header 1

Input 3 trailer

Input 4 header 1

Input 4 trailer

Slink input 1

data

Slink input 2

data

Slink input 3

data

Slink input 4

data

Input 1 header 2

End of fragm

ent

Input 2 header 2

Slink merger output

End of fragm

ent

Input 3 header 2

End of fragm

ent

Input 4 header 2

End of fragm

ent

Reces m

erger head

er 1

Merger header 1

Reces 1

Reces 2

Reces 3Reces merger

Slink merger

• Reces merger and Slink merger firmwares are identical

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Cluster

Taxi inputs

AUX cardSlink outputTwo Taxi mezz cards

Hotlink mezz cardHotlink LVDS mezz card

Hotlink LVDS input

Hotlink input

ISOLIST data

CLIST data

• Receives data from 7 Taxi fibers, 6 Hotlink fibers and 1 LVDS• Saves data to input DAQ buffers• Runs algorithm on ISOLIST and CLIST data• Creates individual Slink packages for ISOLIST and CLIST data after algorithm• Merges ISOLIST and CLIST Slink formatted data• Creates one Slink package and saves it to output DAQ buffer• Sends data out from P3 - AUX card - Slink

Status- CLIST and ISOLIST inputs tested in beam- ISOLIST algorithm and Slink formatting ready for teststand testing- CLIST algorithm and Slink formatting under development- Cluster data merging under development

Firmware for Cluster input and algorithm done by Vadim, more on Vadim’s talk

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Muon

• Receives data from 16 Hotlink fibers, XTRP input and L1 trigger input• Saves data to input DAQ buffers• Zero suppresses Muon data• Merges Muon, XTRP and L1T data• Creates one Slink package and saves it to output DAQ buffer• Sends data out from P3 - AUX card - Slink

Hotlink inputsAUX cardSlink output

Four HotlinkMezz cards

L1T input

XTRP input

Status- Missing L1 trigger input- Firmware needs more work on timing optimizing and modularization- Teststand testing ongoing

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SVT

• Receives SVT data

• Saves data to input DAQ buffer

• Creates one Slink package

• Saves Slink formatted data to output DAQ buffer

• Sends data out from P3 - AUX card – Slink

• Measures SVT and SVX latencies

(time from L1A to BOE/EOE)

AUX cardSlink output

SVX EOE input

SVT input

Status- A lot of teststand testing done- Beam tests ongoing

To do- Only send data needed for L2 algorithm

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L2toTS

• Waits for L1A and data from CPU decision (or L1 trigger input)• Adjustable delay for L2 decision to TS• Sends L2A or L2R or L2TO to TS• Finishes handshake with TS and rearms for next event• Checks buffernumber and bunch count• Saves CPU decision data to DAQ RAM

CDF signalsSlink input

Slink mezz card

Interface to TS

Decision

Handshaking

L1ABuffernumberB0

Status- Teststand tests ongoing

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null

Read L1Aand Decsn

Wait GL2R

[L1AFIFOEmpty = ‘0‘ and DecsnFIFOEmpty = ‘0’]L1AFIFORead <= '1'DecsnFIFORead <= '1'

[DecsnL2A = '1‘and DescnL2TO = ‘0’]L2A <= '1'

[GL2A = '0' and GL2R = '0‘]L2A <= '0'L2R <= '0'L2ACK <= '0'

TS handshake statemachine

Send ACK

L1AFIFORead <= '0'DecsnFIFORead <= '0'

[DecsnL2R = '1‘and DescnL2TO = ‘0’]L2R <= '1'

[GL2A = '1‘]L2ACK <= '1'

Wait GL2A

[GL2R = '1‘]L2ACK <= '1'

Run Timer

Check Decsn

[TimerReady = ‘0‘]




RunTimer <= ‘1'

RunTimer <= ‘0'

Wait L2TO

[DescnL2TO = ‘1’]L2TO <= '1'

[GL2A = '1‘ and GL2R = '1‘]L2ACK <= '1'

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• One unified design that works for all firmwares

• Each FPGA has two DAQ RAMs and two number of word registers (usage varies)

• Each FPGA has common control and status registers (usage varies)

• Registers for firmware version and DAQ software version

• IDPROM on Control FPGA for each Pulsar board

DAQ1

DAQ2

DAQ1

DAQ2

DAQ1

DAQ2

DataIO FPGA 1

DataIO FPGA 2

Control FPGA

New VME interface

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New VME interfaceControl FPGAFirmware version YY000000 (R)Reset YY000004 (W)DAQ SW version YY000008 (R/W)Control register 1 YY00000C (R/W)Status register 1 YY000010 (R)Pulse 1 YY000014 (W)Control register 2 YY000018 (R/W)Control register 3 YY00001C (R/W)Status register 2 YY000020 (R)

IDPROM YY100000 – YY10007C (R)VME address map (user guide) YY100100 – YY1????? (R)

DataIO 1 FPGAFirmware version YY080000 (R)Reset YY080004 (W)Control register 1 YY080008 (R/W)Control register 2 YY08000C (R/W)Status register 1 YY080010 (R)Pulse 1 YY080014 (W)Control register 3 YY080018 (R/W)Control register 4 YY08001C (R/W)Status register 2 YY080020 (R)

VME address map (user guide) YY100100 – YY1????? (R)

DataIO 2 FPGAFirmware version YY0C0000 (R)Reset YY0C0004 (W)Control register 1 YY0C0008 (R/W)Control register 2 YY0C000C (R/W)Status register 1 YY0C0010 (R)Pulse 1 YY0C0014 (W)Control register 3 YY0C0018 (R/W)Control register 4 YY0C001C (R/W)Status register 2 YY0C0020 (R)

VME address map (user guide) YY100100 – YY1????? (R)

Firmware ID + Date + Version number 8-bits 20-bits 4-bits

Example:Slink merger DataIO 02/20/04 first versionHex: 01402200

Firmware IDs01 DataIO Slink merger02 Control Slink merger03 DataIO Muon04 Control Muon05 Control SVT06 DataIO CLIST07 DataIO ISOLIST08 DataIO Reces09 DataIO L2toTS0A Control L2toTS

A1 DataIO Muon TXA2 Control Muon TXA3 DataIO Reces TXA4 DataIO ISOLIST TXA5 DataIO CLIST TXA6 Control SVT TX

Firmware version

Common address map

YY = VMEaddress bits 31..24. These bits not used by firmware.

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Slink merger VME registers

Control FPGAName Address Description Databits DataFirmware version YY000000 (R) Firmware version 31…0 0x02405140Reset YY000004 (W) Reset FPGA - -DAQ SW version YY000008 (R/W) DAQ SW version 31…0 Power-up value: 0Control register 1 YY00000C (R/W) Bunch Count Shift 7…0 Power-up value: 41Status register 1 YY000010 (R) Not used 31…0 0x00c0ffeePulse 1 YY000014 (W) Not used - -Control register 2 YY000018 (R/W) Input selection 3…0 Power-up value: 0 (all enabled)Control register 3 YY00001C (R/W) Not used 31…0 Power-up value: 0Status register 2 YY000020 (R) Not used 31…0 0xdeadbeef

IDPROM YY100000 – YY10007C (R) IDPROM 31…24VME address map YY100100 – YY1????? (R) Not used - -

Input selectionYY000018Bit 0: Input 1Bit 1: Input 2Bit 2: Input 3Bit 3: Input 4High = disableLow = enablePower-up = all enabled

IDPROMYY100000 0YY100004 0YY100008 xYY10000C xYY100010 YY100014 0YY100018 8 YY10001C 1 YY100020YY100024 P YY100028 U YY10002C LYY100030 S YY100034 A YY100038 R

YY10003CYY100040 S YY100044 LYY100048 I YY10004C NYY100050 KYY100054 YY100058 MYY10005C EYY100060 RYY100064 GYY100068 EYY10006C RYY100070 YY100074 YY100078YY10007C

New VME interface


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Boardtype Description081 L2 Pulsar Muon/XTRP Rx IIa083 L2 Pulsar SVT Road Warrior085 L2 Pulsar Muon/XTRP/L1 Tx or SVT XTRP-emu086 L2 Pulsar Muon/XTRP/L1 Rx IIb087 L2 Pulsar RECES Tx088 L2 Pulsar RECES Rx089 L2 Pulsar Cluster/PreFred Tx090 L2 Pulsar Cluster/PreFred Rx091 L2 Pulsar SVT Tx092 L2 Pulsar SVT Rx093 L2 Pulsar Merger Tx094 L2 Pulsar Merger Rx095 L2 Pulsar L2TS Tx096 L2 Pulsar L2TS097 L2 Pulsar L1 Scaler098 L2 Pulsar SVT TF099 L2 Pulsar test one100 L2 Pulsar test two101 L2 Pulsar Stereo Tx102 L2 Pulsar Stereo Rx

YY100000 0YY100004 0YY100008 xYY10000C xYY100010 YY100014 0YY100018 8 YY10001C 1 YY100020YY100024 P YY100028 U YY10002C L YY100030 S YY100034 A YY100038 R

YY10003CYY100040 S YY100044 L YY100048 I YY10004C NYY100050 KYY100054 YY100058 MYY10005C EYY100060 RYY100064 GYY100068 EYY10006C RYY100070 YY100074 YY100078YY10007C

Serial #

Board typeFirmwarename

IDPROM

New VME interfaceIDPROM

• Part of the serial number is controlled from an on board dip switch

• IDPROM VME interface is identical on all firmwares, only memory input file (.mif) needs to be firmware specific

• All L2 Pulsars have been given indivitual board types

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Control DAQ 2ReadoutBuffer 0 YY820000 Buffer 1 YY920000 Buffer 2 YYA20000Buffer 3 YYB20000

Word countBuffer 0 YY000804Buffer 1 YY000904Buffer 2 YY000A04Buffer 3 YY000B04

Word count

Buffer 0 YY000800Buffer 1 YY000900Buffer 2 YY000A00Buffer 3 YY000B00

ReadoutBuffer 0 YY800000Buffer 1 YY900000Buffer 2 YYA00000Buffer 3 YYB00000

Control DAQ 1 (Pulsar output)

Buffer 0 YY880000Buffer 1 YY980000Buffer 2 YYA80000Buffer 3 YYB80000

Readout

Buffer 0 YY8E0000Buffer 1 YY9E0000Buffer 2 YYAE0000Buffer 3 YYBE0000


Buffer 0 YY0C0800Buffer 1 YY0C0900Buffer 2 YY0C0A00Buffer 3 YY0C0B00

DataIO1 DAQ 1

Buffer 0 YY8A0000Buffer 1 YY9A0000 Buffer 2 YYAA0000Buffer 3 YYBA0000

DataIO1 DAQ 2Readout


Word count

Word count

DataIO2 DAQ 1

Buffer 0 YY8C0000Buffer 1 YY9C0000Buffer 2 YYAC0000Buffer 3 YYBC0000

Readout


DataIO2 DAQ 2Readout

Word count

Word count

Readout FPGA / DAQ selection bits

VMEaddress bits 18, 1919 18 0 0 Control 1 0 DataIO 1 1 1 DataIO 2

New readout VME address map

FPGA selectionVMEaddress bit 1717 0 DAQ 1 1 DAQ 2

DAQ selection

DAQ SW version registerYY000008 (R/W)

Please write CDF00001 into each board.Can be used as software version number.


New VME interface

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New readout VME address mapNew VME interface

Ch 0Buffer 0 YY880000Buffer 1 YY980000Buffer 2 YYA80000Buffer 3 YYB80000




Readout


DataIO1 DAQ 1


Word countDataIO2 DAQ 1Word count





Ch 0Buffer 0 YY8C0000Buffer 1 YY9C0000Buffer 2 YYAC0000Buffer 3 YYBC0000




ReadoutCh 4Buffer 0 YY8C0400Buffer 1 YY9C0400Buffer 2 YYAC0400Buffer 3 YYBC0400





Special case when NCHANNEL > 1 (for Cluster)

1 Pulsar firmware status June 11th, 2004 Slink format Transmitter firmware Transmitter firmware status Receiver firmware overview Receiver firmware status.

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