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ECE357: Introduction to VLSI CAD Prof. Hai Zhou Electrical Engineering & Computer Science Northwestern University 1 www.jntuworld.com www.jntuworld.com
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Page 1: 1 Introductionof VLSI

www.jntuworld.comECE357: Introduction to VLSI CAD

Prof. Hai Zhou

Electrical Engineering & Computer Science

Northwestern University

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Page 2: 1 Introductionof VLSI

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Logistics

• Time & Location: MWF 11-11:50 TECH L160

• Instructor: Hai Zhou [email protected]

• Office: L461

• Office Hours: W 3-5P

• Teaching Assistant: Chuan Lin

• Texts:

VLSI Physical Design Automation: Theory & Practice, Sait

& Youssef, World Scientific, 1999.

• Reference:

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Page 3: 1 Introductionof VLSI

www.jntuworld.comAn Introduction to VLSI Physical Design, Sarrafzadeh &

Wong, McGraw Hill, 1996.

• Grading: Participation-10% Project-30% Midterm-30%

Homework-30%

• Homework must be turned in before class on each due date,

late: -40% per day

• Course homepage:

www.ece.northwestern.edu/~haizhou/ece357

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Page 4: 1 Introductionof VLSI

www.jntuworld.comWhat can you expect from the course

• Understand modern VLSI design flows (but not the details

of tools)

• Understand the physical design problem

• Familiar with the stages and basic algorithms in physical

design

• Improve your capability to design algorithms to solve

problems

• Improve your capability to think and reason

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Page 5: 1 Introductionof VLSI

www.jntuworld.comWhat do I expect from you

• Active and critical participation

– speed me up or slow me down if my pace mismatches

yours

– “Your role is not one of sponges, but one of whetstones;

only then the spark of intellectual excitement can

continue to jump over”

• Read the textbook

• Do your homeworks

– You can discuss homework with your classmates, but

need to write down solutions independently

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Page 6: 1 Introductionof VLSI

www.jntuworld.comVLSI (Very Large Scale Integrated) chips

• VLSI chips are everywhere

– computers

– commercial electronics: TV sets, DVD, VCR, ...

– voice and data communication networks

– automobiles

• VLSI chips are artifacts

– they are produced according to our will ...

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Page 7: 1 Introductionof VLSI

www.jntuworld.comDesign: the most challenging human activity

• Design is a process of creating a structure to fulfill a

requirement

• Brain power is the scarcest resource

– Delegate as much as possible to computers–CAD

• Avoid two extreme views:

– Everything manual: impossible–millions of gates

– Everything computer: impossible either

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Page 8: 1 Introductionof VLSI

www.jntuworld.comDesign is always difficult

A main task of a designer is to manage complexity

• Silicon complexity: physical effects no longer be ignored

– resistive and cross-coupled interconnects; signal

integrity; weak and faster gates

– reliability; manufacturability

• System complexity: more functionality in less time

– gap between design and fabrication capabilities

– desire for system-on-chip (SOC)

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Page 9: 1 Introductionof VLSI

www.jntuworld.comCAD: A tale of two designs

• Target–hardware design

– How to create a structure on silicon to implement a

function

• Aid–software design (programming)

– How to create an algorithm to solve a design problem

• Be conscious of their similarities and differences

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Page 10: 1 Introductionof VLSI

www.jntuworld.comEmphasis of the course

• Design flow

– Understand how design process is decomposed into

many stages

– What are the problems need to be solved in each stage

• Algorithms

– Understand how an algorithm solves a design problem

– Consider the possibility to extend it

• Be conscious and try to improve problem solving skills

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Page 11: 1 Introductionof VLSI

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Basics of MOS Devices

• The most popular VLSI technology: MOS(Metal-Oxide-Semiconductor).

• CMOS (Complementary MOS) dominates nMOS andpMOS, due to CMOS’s lower power dissipation, highregularity, etc.

• Physical structure of MOS transistors and their schematicicons: nMOS, pMOS.

• Layout of basic devices:

– CMOS inverter

– CMOS NAND gate

– CMOS NOR gate

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Page 12: 1 Introductionof VLSI

www.jntuworld.comMOS Transistors

n n

p−substrate

drain sourcegate

insulator (SiO )2

substrate

drain source

gate

n−transistorschematic icon

conductor (polysilicon)

diffusion

The nMOS switch passes "0" well.

drain sourcegate

insulator (SiO )2

substrate

drain source

gate

schematic icon

conductor (polysilicon)

diffusion

pp

n−substrate

p−transistor

The pMOS switch passes "1" well.

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Page 13: 1 Introductionof VLSI

www.jntuworld.comA CMOS Inverter

A B

GND

VDD

Metal Metal−diffusion contact

Diffusion

Polysilicon

A B1 00 1

pMOS transistor

nMOS transistor

A B

p−channel (pMOS)

n−channel (nMOS)

VDD

GND

layout

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Page 14: 1 Introductionof VLSI

www.jntuworld.comA CMOS NAND Gate

A

GND

VDD

Metal

Diffusion

Polysilicon

BC

A B C

0011

0101

AB

VDD

GND

0

C

111

layout

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Page 15: 1 Introductionof VLSI

www.jntuworld.comA CMOS NOR Gate

A B C

0011

0101

A

B

VDD

GND

00

1

0

C

A

GND

VDD

Metal

Diffusion

Polysilicon

BC

layout

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Page 16: 1 Introductionof VLSI

www.jntuworld.comCurrent VLSI design phases

• Synthesis (i.e. specification → implementation)

1. High level synthesis (459 VLSI Algorithmics)

2. Logic synthesis (459 VLSI Algorithmics)

3. Physical design (This course)

• Analysis (implementation → semantics)

– Verification (design verification, implementation

verification)

– Analysis (timing, function, noise, etc.)

– Design rule checking, LVS (Layout Vs. Schematic)

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Page 17: 1 Introductionof VLSI

www.jntuworld.comPhysical Design

• Physical design converts a structural description into a

geometric description.

• Physical design cycle:

1. Circuit partitioning

2. Floorplanning

3. placement, and pin assignment

4. Routing (global and detailed)

5. Compaction

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Page 18: 1 Introductionof VLSI

www.jntuworld.comDesign Styles

Different design styles

Full custom Standard cell Gate array FPGA CPLD SPLD SSI

Issues ofVLSI circuits

Performance Area Cost Time−to−market

Performance, Area efficiency, Cost, Flexibility

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www.jntuworld.comFull Custom Design Style

Data path

ROM/RAM

A/D converter

I/O PLA

Controller

Random logic

I/O padspins

over−the−cell routing

via(contact)

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Page 20: 1 Introductionof VLSI

www.jntuworld.comStandard Cell Design Style

D

D D

A

A

A

A

B

B B

BB

C

C

Cell A Cell B

Cell C Cell D Feedthrough Cell

library cells

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Page 21: 1 Introductionof VLSI

www.jntuworld.comGate Array Design Style

I/O pads

pins

prefabricated transistor array

customized wiring

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Page 22: 1 Introductionof VLSI

www.jntuworld.comFPGA Design Style

logicblocks

routing tracks

switchesPrefabricated all chip components

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Page 23: 1 Introductionof VLSI

www.jntuworld.comSSI/SPLD Design Style

x1 1y x2 y2 x3 y3 x4 y4

F= i=14 xi yi

x1

1y

x2

y2

x3

y3

x4

y4

F

GND

Vcc VccVcc

GNDGND

74LS86 74LS0074LS02

x1

1y

x2

y2

x3

y3

x4

y4

F

AND array

OR array

F

x1 1y x2 y2

x3

y3

x4

y4

(a) 4−bit comparator. (b) SSI implementation.

(c) SPLD (PLA) implementation. (d) Gate array implementation.

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Page 24: 1 Introductionof VLSI

www.jntuworld.comComparisons of Design Styles

Full Standard Gatecustom cell array FPGA SPLD

Cell size variable fixed height∗ fixed fixed fixedCell type variable variable fixed programmable programmableCell placement variable in row fixed fixed fixedInterconnections variable variable variable programmable programmable

* Uneven height cells are also used.

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Page 25: 1 Introductionof VLSI

www.jntuworld.comComparisons of Design Styles

Full Standard Gatecustom cell array FPGA SPLD

Fabrication time − − − − − + +++ ++Packing density +++ ++ + − − − − −Unit cost in large quantity +++ ++ + − − −Unit cost in small quantity − − − − − + +++ +Easy design and simulation − − − − − − ++ +Easy design change − − − − − − ++ ++Accuracy of timing simulation − − − + +Chip speed +++ ++ + − −−

+ desirable− not desirable

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Page 26: 1 Introductionof VLSI

www.jntuworld.comDesign-Style Trade-offs

1 10 102 103104 105 106

1

10

102

103

optimal solution

SPLD’sCPLD’s

FPGA’s

SSI’s

Logic Capacity (Gates)

Turnaround Time (Days)

Fullcustom

104

107

semi−custom

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www.jntuworld.comAlgorithms 101

• Algorithm: a finite step-by-step procedure to solve a

problem

• Requirements:

– Unambiguity: can even be followed by a machine

– Basic: each step is among a given primitives

– Finite: it will terminate for every possible input

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www.jntuworld.comA game

• An ECE major is sitting on the Northwestern beach and

gets thirsty, she knows that there is an ice-cream booth

along the shore of Lake Michigan but does not know

where–not even north or south. How can she find the

booth in the shortest distance?

• Primitives: walking a distance, turning around, etc.

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Page 29: 1 Introductionof VLSI

www.jntuworld.comA first solution

• Select a direction, say north, and keep going until find the

booth

• Suppose the booth is to the south, she will never stop... of

course, with the assumption she follows a straight line, not

lake shore or on earth

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Page 30: 1 Introductionof VLSI

www.jntuworld.comAnother solution

• Set the place she is sitting as the origin

• Search to south 1 yard, if not find, turn to north

• Search to north 1 yard, if not find, turn to south

• Search to south 2 yard, if not find, turn to north

• Search to north 2 yard, if not find, turn to south

• ... (follow the above pattern in geometric sequence 1, 2, 4,

8, ...)

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Page 31: 1 Introductionof VLSI

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• n = −1;

• While (not find) do

– n = n+ 1;

– Search to south 2n, and turn;

– Search to north 2n, and turn;

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Page 32: 1 Introductionof VLSI

www.jntuworld.comCorrectness proof

• Each time when the while loop is finished, the range from

south 2n to north 2n is searched. Based on the fact that

the booth is at a constant distance x from the origin, it will

be within a range from south 2N to north 2N for some N .

With n to increment in each loop, we will find the booth in

finite time.

• Is this the fastest (or shortest) way to find the booth?

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Analysis of algorithm

• Observation: the traveled distance depends on where is the

booth

• Suppose the distance between the booth and the origin is x

• When the algorithm stops, we should have 2n ≥ x but

2n−1 < x

• The distance traveled is

3 · 2n + 2(2 · 2n−1 + 2 · 2n−2 + · · ·+ 2) ≤ 7 · 2n

• which is smaller than 14x

• We know that the lower bound is x, can we do better?

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Page 34: 1 Introductionof VLSI

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• Two resources: running time and storage

• They are dependent on inputs: expressed as functions of

input size

– Why input size: lower bound (at least read it once)

• Big-Oh notation: f(n) = O(g(n)) if there exist constants n0

and c such that for all n > n0, f(n) ≤ c · g(n).

– Make our life easy: is it 13x instead of 14x in our game

– The solution is asymptotically optimal for our game

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Page 35: 1 Introductionof VLSI

www.jntuworld.comTime complexity of an algorithm

• Run-time comparison: 1000 MIPS (Yr: 200x), 1 instr. /op.

Time Big-Oh n = 10 n = 100 n = 103 n = 106

500 O(1) 5× 10−7 sec 5× 10−7 sec 5× 10−7 sec 5× 10−7 sec3n O(n) 3× 10−8 sec 3× 10−7 sec 3× 10−6 sec 0.003 secn logn O(n logn) 3× 10−8 sec 2× 10−7 sec 3× 10−6 sec 0.006 secn2 O(n2) 1× 10−7 sec 1× 10−5 sec 0.001 sec 16.7 minn3 O(n3) 1× 10−6 sec 0.001 sec 1 sec 3× 105 cent.2n O(2n) 1× 10−6 sec 3× 1017 cent. - -n! O(n!) 0.003 sec - - -

• Polynomial-time complexity: O(p(n)), where n is the input

size and p(n) is a polynomial function of n.

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Complexity of a problem

• Given a problem, what is the running time of the fastest

algorithm for it?

• Upper bound: easy–find an algorithm with less time

• Lower bound: hard–every algorithm requires more time

• P: set of problems solvable in polynomial time

• NP(Nondeterministic P): set of problems whose solution

can be proved in polynomial time

• Millennium open problem: NP 6= P?

– Fact: there are a set of problems in NP resisting any

polynomial solution for a long time (40 years)

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Page 37: 1 Introductionof VLSI

www.jntuworld.comNP-complete and NP-hard

• Cook 1970: If the problem of boolean satisfiability can be

solved in poly. time, so can all problems in NP.

• Such a problem with this property is called NP-hard.

• If a NP-hard problem is in NP, it is called NP-complete.

• Karp 1971: Many other problems resisting poly. solutions

are NP-complete.

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How to deal with a hard problem

• Prove the problem is NP-complete:

1. The problem is in NP (i.e. solution can be proved in

poly. time)

2. It is NP-hard (by polynomial reducing a NP-complete

problem to it)

• Solve NP-hard problems:

– Exponential algorithm (feasible only when the problem

size is small)

∗ Pseudo-polynomial time algorithms

– Restriction: work on a subset of the input space

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Page 39: 1 Introductionof VLSI

www.jntuworld.com– Approximation algorithms: get a provable

close-to-optimal solution

– Heuristics: get a as good as possible solution

– Randomized algorithm: get the solution with high

probability

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Algorithmic Paradigms

• Divide and conquer: divide a problem into sub-problems,solve sub-problems, and combine them to construct asolution.

– Greedy algorithm: optimal solutions to sub-problems willgive optimal solution to the whole problem.

– Dynamic programming: solutions to a larger problem areconstructed from a set of solutions to its sub-problems.

• Mathematical programming: a system of optimizing anobjective function under constraints functions.

• Simulated annealing: an adaptive, iterative,non-deterministic algorithm that allows “uphill” moves toescape from local optima.

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Page 41: 1 Introductionof VLSI

www.jntuworld.com• Branch and bound: a search technique with pruning.

• Exhaustive search: search the entire solution space.

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