1 4446 Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology Serial Interface.

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4446 Design of Microprocessor-Based Systems

Dr. Esam Al_QarallehCE Department

Princess Sumaya University for Technology

Serial Interface

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External Interface• Two ways of interfacing I/O devices

– Serial • Cheaper

• Slower

– Parallel• Faster

• Data skew

• Limited to small distances

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External Interface (cont’d)Two basic modes of data transmission

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External Interface (cont’d)• Serial transmission

– Asynchronous• Each byte is encoded for transmission

– Start and stop bits

• No need for sender and receiver synchronization

– Synchronous• Sender and receiver must synchronize

– Done in hardware using phase locked loops (PLLs)

• Block of data can be sent

• More efficient– Less overhead than asynchronous transmission

• Expensive

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External Interface (cont’d)

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External Interface (cont’d)Asynchronous transmission

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External Interface (cont’d)

• EIA-232 serial interface– Low-speed serial transmission

– Adopted by Electronics Industry Association (EIA)

• Popularly known by its predecessor RS-232

– It uses a 9-pin connector DB-9• Uses 8 signals

– Typically used to connect a modem to a computer

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External Interface (cont’d)• Transmission protocol uses three phases

– Connection setup• Computer A asserts DTE (Data Terminal Equipment) Ready

– Transmits phone# via Transmit Data line (pin 2)

• Modem B alerts its computer via Ring Indicator (pin 9)– Computer B asserts DTE Ready (pin 4)– Modem B generates carrier and turns its DCE (Data Communication

Equipment) Ready

• Modem A detects the carrier signal from modem B– Modem A alters its computer via Carrier Detect (pin 1)– Turns its DCE Ready

– Data transmission• Done by handshaking using

– request-to-send (RTS) and clear-to-send (CTS) signals– Connection termination

• Done by deactivating RTS

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Serial Data Transfer Asynchronous v.s. Synchronous

— Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication — Synchronous transfer does not transfer extra bits. However, it requires clock signal

Frame

Startbit B0 B1 B2 B3 B4 B5 B6

ParityStop bits

AsynchronousData transfer

SynchronousData transfer

clk

data

B0 B1 B2 B3 B4 B5

data

Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).

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8251 USART Interface

A7A6A5A4A3A2A1

IO/M

D[7:0]

RD RD

WR WRA0 C/D

CLK CLKTxC

RxC

TxD

RxD

8251 RS232

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Programming 8251

8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Stop bits

00: invalid01: 1 bit10: 1.5 bits11: 2 bits

Parity0: odd1: even

Parity enable0: disable1: enable

Character length

00: 5 bits01: 6 bits10: 7 bits11: 8 bits

Baud Rate

00: Syn. Mode01: x1 clock10: x16 clock11: x64 clock

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Programming 8251

8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enableDTR: data terminal ready, DTR pin will be lowRxE: receiver enableSBPRK: send break character, TxD pin will be lowER: error resetRTS: request to send, CTS pin will be lowIR: internal resetEH: enter hunt mode

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Programming 8251

8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register

TxRDY: transmit readyRxRDY: receiver readyTxEMPTY: transmitter emptyPE: parity errorOE: overrun errorFE: framing errorSYNDET: sync. character detectedDSR: data set ready

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Simple Serial I/O Procedures

Read

start

Check RxRDY

Is it logic 1?

Read data register*

end

Yes

No

* This clears RxRDY

Write

start

Check TxRDY

Is it logic 1?

Write data register*

end

Yes

No

* This clears TxRDY

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Errors

– Parity error: Received data has wrong error -- transmission bit flip due to noise.

– Framing error: Start and stop bits not in their proper places.

• This usually results if the receiver is receiving data at the incorrect baud rate.  

– Overrun error: Data has overrun the internal receiver FIFO buffer.

• Software is failing to read the data from the FIFO.