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01. 8212, 8282, 8286

Apr 21, 2015

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,2011

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?

MCS85 (MCS86)

DMA

I. 1 2 3

8- - /8- : 8212 : 8282/8283 bus : 8286/8287

? Intel MCS-80/85 Family Users Manual (Chapter 6)

8212

8212 - (1) , 8- I/O MPS85. - -, (gated buffers) VIL(max) = 0.85V VIH(min) = 2V VOL(max) = 0.45V VOH(min) = 3.65V VCC=5V

8212

GND

8212 (2)(Strobe Signal) STB (Clear Signal) 8 DI0 DI7 (Data In) MD DS1 DS2 (Mode) CLR INT (Interrupt) 8

8212

DO0 DO7 (Data Out)

(Device Select)

8212 (1) (Control and Device Selection Logic) 2DI0 DI1

+

Service Request FF

INT

LATCH 1 LATCH 2

BUFFER 1 BUFFER 2

DO0 DO1

. . .DI7

. . .BUFFER 8DO7

LATCH 8

1

3-

: -LEVEL SENSITIVE . : EDGETRIGGERED . :

Clk = 1 then Qn+1 = D Clk = 0 then Qn+1 = Qn clk D Q(latch) Q(flop)

Clk = then Qn+1 = D Clk = otherwise, then Qn+1=Qn

2

EN D 1 C R Q

1DO0

DI0

DI1

D 2 C R

Q

DO1

. . .DI7D

EN=1 EN=0

. . .Q 8 C R

DO=Q . DO=Z . .DO7

C=1 C=0

Qn+1=D Qn+1=Qn

3

2 Device Selection Logic(DS1DS2)DS1 1 DS2

5 D C S Q

Service Request Flip FlopINT 8

FF

7 MD STB 2 6 3 D 1 C R Q

EN

DO1

DI1

Control Logic

CLR

4

2 (1)DS1 DS2 MD STB

5 D C S Q

FF INT 8 7

01

1 12 6 3

1 1

EN

1D 1 C R Q DO1

DI1

Q=DCLR 1 4

1

DO1=DI1

2 (2)DS1 DS2 MD STB

5 D C S Q

FF INT 8 7

01

1 12 6 3

1 0 1 1D

EN

Q 1 R

DO1

DI1

1 1 1

C

Q=D DO1=DI1

CLR

1

4

2 (3)DS1 DS2 MD STB

5 D C S Q

FF INT 8 7

01

1 12 6 3

1 0 0 0D

EN

Q 1 R

DO1

DI1

0 0

C

Data Latch State4

Qn+1=Qn DO1=Qn

CLR

1

2 (4)DS1 DS2 MD STB

5 D C S Q

FF INT 8 7

01

0 02 6 3

0 0 0 0D

EN

0Q 1 R DO1

DI1

0 0

C

Data Latch State4

DO1=Z Qn+1=Qn

CLR

1

2 (5)DS1 DS2 MD STB

5 D C S Q

FF INT 8 7

01

0 02 6 3

0 0 1 1D

EN

0Q 1 R DO1

DI1

1 1 1

C

DO1=Z Qn+1=D

CLR

1

4

8212 (1)STB 0 1 0 1 0 1 0 1 MD 0 0 1 1 0 0 1 1 DS1DS2 0 0 0 0 1 1 1 1

Data OUT3-State 3-State Data Latch Data Latch Data Latch Data In Data In Data In

1

2 INT (1)5

D C S Q

INT 8

FF

DS1 1 DS2 7 MD STB 2 6 3

INT=0 :

Porta1out=1 QSR-FF=0CLR 4

2 INT (2)

05 D S Q

1INT 8

DS1 DS2 MD STB

01

C

FF

1 17 2 6 3

1

0

?!

CLR

4

2 INT (3)5 D S Q INT 8

DS1 DS2 MD STB

11

C

FF

0 07 2 6 3

0 0

a SR FF

CLR

4

8212 (2) 8212 :

CLR 0 0 1 1 1 1

DS1DS2 STB 0 1 1 1 0 1 0 0 0 0

SR 1 1 0 1 1 1

INT 1 0 0 0 1 0

SR FF : . !

8212(1) a (3-state Gated Buffer ) (2) (Bi-Directional Bus Driver) (3) (Interrupting Input Port) (4) (Interrupt Instruction Port) (5) (Output Port with hand-shaking) (6) (8085 Address Latch)

8212- (1) INPUT STROBE STB

SYSTEM INPUT

8212

CLR DS1 MD

INT DS2

GND

DATA BUS

8

8

8212- (2) STB OUTPUT FLAG

DATA BUS

8

8

8212

SYSTEM OUTPUT

INT DS2 MD

CLR DS1

VCC

(1) (3-state Gated Buffer )

VCC8INPUT DATA

STB

STB=1; CLR=1 MD=0 8OUTPUT DATA

8212

CLR

DS1 DS2 Logic =TRUE EN=1 DataOut=DataIn GND DS1 DS2 Logic =FALSE EN=0 DataOut=Z

Gating Control (DS1DS2)

(2) (Bi-Directional Bus Driver) 1DATA BUS STB

VCCDATA BUS

8212CLR

GND 2STB

8212 Data Bus ControlCLR

GND

(2) (Bi-Directional Bus Driver)- (1)

EN=0DATA BUS

STB

Z

VCCDATA BUS

8212 1CLR

1 GND DataOut =DataIn Data Bus ControlSTB

8212 2CLR

EN=1

GND

(2) (Bi-Directional Bus Driver)- (2)

EN=1DATA BUS

STB

VCCDATA BUS

8212 1CLR

DataOut =DataIn

0 GND

ZData Bus Control

STB

8212 2CLR

EN=0

GND

(3) (Interrupting Input Port)INPUT STROBE STB

SYSTEM INPUT

8

8

8212

SYSTEM RESET

CLR DS1 MD

INT DS2

Port Selection (DS1DS2)

GND

DATA BUS

to CPU interrupt input

(4) (Interrupt Instruction Port) VCCSTB

8 RESTART INSTRUCTION (RST 0->RST 7)

8

8212

CLR DS1 MD DS2

DS1 Port Selection Interrupt Acknowledge

GND

DATA BUS

(5) (Output Port with hand-shaking)OUTPUT STROBE STB

DATA BUS

8

8

8212

SYSTEM OUTPUT

INT SYSTEM INTERRUPT DS2 MD

CLR DS1

SYSTEM RESET

Vcc

Port Selection (Latch Control) (DS1DS2)

(6) (8085 Low-Order Address Latch) 8085 - ( ) 8 .

?

8085

ADO AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALEDI1 DI7 CLR DS2 STB

DO D1 D2 D3 D4 D5 D6 D7 Vcc

DO1

8212MD DS1

DO7

Vcc

GND

DATA BUS

8282/8283

8282/8283 - (1) 8 - - - -,

8282

VIL(max) = 0.8V VIH(min) = 2V VOL(max) = 0.5V VOH(min) = 2.4V

8283

8282/8283 (2)

8 DI0 DI7 (Data In) OE STB

8

8282

DO0 DO7 (Data Out) DO=DI (8282) DO=DI (8283)

Output Strobe ( Enable )

8282 (1)DI0

LATCH 1

BUFFER 1

DO0

DI1

LATCH 2

BUFFER 2

DO1

. . .DI7

. . .BUFFER 8DO7

LATCH 8

STB

8282 (2) DI0 D Q DO0

CLK

STB=1 STB=0 STB

Qn+1=D Qn+1=Qn OE=1 OE=0 OE DO1=Z DO1=Qn+1

8282

INPUTS STB

OE

OUTPUTS

8286/8287 (Octal Bus Transceiver)

8286/8287 - (1) 8- - MCS.

8286

VIL(max) = 0.8(0.9)V VIH(min) = 2V VOL(max) = 0.5V VOH(min) = 2.4V

8287

8286 (2)

8 A0 A7 Local Bus Data

8

8286

B0 B7 System Bus Data

OE

T

Output Transmit (Input) Enable

8286 (3)01

2 EN1 EN2

B0

OE

T=1OE=0

T

EN2=0 EN1=1

B:out A:in T=0OE=0

EN1=0 EN2=1

A:out B:in

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