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-BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation of H.264 Video Encoder
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-BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

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Page 1: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

-BY KUSHAL KUNIGAL UNDER GUIDANCE OF

DR. K.R.RAO.

SPRING 2011,

ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON

FPGA Implementation of H.264 Video Encoder

Page 2: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Proposal

This project is based on the implementation of H.264 Video encoder and the Algorithms for evaluating the Transform and quantization Suitable for high speed implementation on FPGA/ASIC.

Page 3: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Modified Encoder Hardware Design:

Fig 1: Modified Encoder Hardware Design [3].

Page 4: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Description of Test Data

The encoder will be used to encode a frame from a video sequence:

30 frames/second.Each frame is 176 x 144 pixels (QCIF Resolution, very typical for low bit-rate video contents in cell phones).

Page 5: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Description of Test Data

Reference Frame

Fig 2: Reference frame 1 [4].

Page 6: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Description of Test Data

Current Frame

Fig 3: Current frame 2 [4].

Page 7: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Residual Frame

Fig 4: Residual of current frame [4].

Page 8: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Different Stages in designing H.264 Encoder

Motion EstimationMotion CompensationDiscrete Cosine TransformQuantization

Page 9: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Motion Estimation

Fig 5: The principle of block matching motion estimation algorithm is finding the best matching block in the searching area of a reference frame for each macroblock in the original frame.

Page 10: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

four-step search

Step 1: A macro block that is the “best match” is found from a nine-checking-points pattern on a 5x5 window located at the center of the 15 x 15 search area (Figure 5a).

Decision: If the “best matched” macro block is found at the center of the search window, go to Step 3 otherwise go to Step 2.

Page 11: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Four-step search

Step 2: The search-window size is maintained at 5 x 5. However, the search patter will depend on the position of the previous “best matched” macro block location.  a. If the previous “best matched” macro block is located at the corner of the search window, fiveadditional checking points (Figure 5b) are used.

Page 12: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Four-step search

b. If the previous “best matched” macro block is located at the middle of the horizontal or vertical axis of the previous search window, three additional checking points (Figure 5c) are used. Decision: If the “best matched” macro block is found at the center of the search window, go to Step 3; otherwise go to Step 2. Step 3,4: The search window is reduced to 3 x 3 (Figure 5d) and the direction of the overall motion vector is considered as the “best matched” macro block is among these nine macro blocks.

Page 13: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

4-Step Search

Check points for motion estimation4x4 macroblock

A 20x20 pixel search range divided up by 4x4 pixel search

Fig 6a: A 20x20 pixel search range divided up by 4x4 pixel search [5].

Page 14: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

4-step search

Step 2

Fig 6b: A 20x20 pixel search range with 5 additional checkpoints during step 2 of the four-step search algorithm [5].

Page 15: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

4-step search

Step 3

Fig 6c: A 20x20 pixel search range with 3 additional checkpoints during step 3 of the four-step search algorithm [5].

Page 16: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

4-step search

Step 4

Fig 6d: A 20x20 pixel search range with 5x5 search window, now reduced to 3x3 during step 4 of the four-step search algorithm [5].

Page 17: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Motion Vector Description

Fig 7. Motion vector description.

Page 18: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Pseudo code

Fig 8: Psuedo code for obtaining predicted frame [6].

Page 19: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Overall view of operations in encoder module

Fig 9: Overall view of operations in encoder module [6].

Page 20: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Websites and References

[1] T. Wiegand, G. J. Sullivan, G. Bjøntegaard, and A. Luthra “Overview of the H.264/AVC Video Coding Standard”, IEEE Trans. on Circuits and Systems for Video Technology vol. 13, no. 7, pp.560–576, July 2003.

[2]Data locality description: http://www.eetimes.com/design/embedded/4007043/How-to-map-the-H-264-AVC-video-standard-onto-an-FPGA-fabric.

[3] N. Keshaveni, S. Ramachandran, K. S. Gurumurthy “Design and FPGA Implementation of Integer Transform and Quantization Processor and Their Inverses for H.264 Video Encoder”, Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT 2009. International Conference on, pp. 646-649, July 2009

[4] I. Richardson, “The H.264 advanced video compression standard”, Wiley, 2nd edition, 2010.

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[5] L. Po, W. C. Ma, “A novel four-step search algorithm for fast block motion estimation”, Circuits and Systems for Video Technology, IEEE Transactions on , vol. 6, no. 3, pp. 313-317, August 1996.

[6] W. I. Choi, B. Jeon, J. Jeong, “Fast motion estimation with modified diamond search for variable motion block sizes”, Image Processing, 2003. ICIP 2003. Proceedings. 2003 International Conference on, vol. 2, no. 2, pp. 11, Sept 2003.

[7] How to map the H.264/AVC video standard onto an FPGA fabric - http://www.eetimes.com/design/embedded/4007043/How-to-map-the-H-264-AVC-video-standard-onto-an-FPGA-fabric.

[8]CODEC Architecture for modules- http://www.drtonygeorge.com/Video/h264/comp_architecture.htm

Websites and References

Page 22: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

[9] Q. Peng and J. Jing, “H.264 System on Chip Design and Verification”, The IEEE 2003 Workshop on Signal Processing Systems(SIPS’03), 2003.

[10] DSP-Enabled efficient motion estimation for Mobile MPEG-4 video encoding- http://www.techonline.com/community/21066.

[11] T. Wiegand, Gary J. Sullivan, G. Bjontegaard, and A. Luthra, "Overview of the H.264/AVC Video Coding Standard", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 560-576, July 2003.

[12] T. Wedi, H. G. Musmann, "Motion- and aliasing-compensated prediction for hybrid video coding," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 577- 586, July 2003.

Websites and References

Page 23: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Websites and references

[13] H. S. Malvar, A. Hallapuro, M. Karczewicz, L. Kerofsky, "Low-complexity transform and quantization in H.264/AVC," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 598- 603, July 2003.

[14] S. Yeping, S. Ting, "Fast Multiple Reference Frame Motion Estimation for H.264/AVC," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 16, no. 3, pp 447 – 452, June 2006.

Page 24: -BY KUSHAL KUNIGAL UNDER GUIDANCE OF DR. K.R.RAO. SPRING 2011, ELECTRICAL ENGINEERING DEPARTMENT, UNIVERSITY OF TEXAS AT ARLINGTON FPGA Implementation.

Websites ans references

[15] ModelSim simulation software: http://model.com/content/modelsim-pe-student-edition-hdl-simulation .